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pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz datasheet product features the pentium ? iii processor is designed for high-performance desktops and for workstations and servers. it is binary compatible with previous intel architecture processors. the pentium iii processor provides great performance for applications running on advanced operating systems such as windows* 98, windows nt and unix*. this is achieved by integrating the best attributes of intel processors the dynamic execution, dual independent bus architecture plus intel mmx? technology and internet streaming simd extentions bringing a new level of performance for systems buyers. the pentium ? iii processor is scaleable to two processors in a multiprocessor system and extends the power of the pentium ? ii processor with performance headroom for business media, communication and internet capabilities. systems based on pentium ? iii processors also include the latest features to simplify system management and lower the cost of ownership for large and small business environments. the pentium ? iii processor offers great performance for todays and tomorrows applications. fc-pga370 package n available in 933, 866, 800eb, 733, 667, 600eb, and 533eb mhz for a 133 mhz system bus n available in 850, 800, 750, 700, 650, 600e, 550e, and 500e mhz for a 100 mhz system bus n system bus frequency at 100 mhz and 133 mhz ("e" denotes support for advanced transfer cache and advanced system buffering; "b" denotes support for a 133mhz system bus where both bus frequencies are available for order per each given core frequency; see table 1 for a summary of features for each line item.) n available in versions that incorporate 256 kb advanced transfer cache (on-die, full speed level 2 (l2) cache with error correcting code (ecc)) n dual independent bus (dib) architecture: separate dedicated external system bus and dedicated internal high-speed cache bus n internet streaming simd extensions for enhanced video, sound and 3d performance n binary compatible with applications running on previous members of the intel microprocessor line n dynamic execution micro architecture n intel processor serial number n power management capabilities n system management mode n multiple low-power states n optimized for 32-bit applications running on advanced 32-bit operating systems n flip chip pin grid array (fc-pga) packaging technology; fc-pga processors deliver high performance with improved handling protection and socketability n integrated high performance 16 kb instruction and 16 kb data, nonblocking, level one cache n 256 kb integrated full speed level two cache allows for low latency on read/store operations n double quad word wide(256bit) cache data bus provides extremely high throughput on read/store operations. n 8-way cache associativity provides improved cache hit rate on reads/store operations. n error-correcting code for system bus data n enables systems which are scaleable for up to two processors may 2000 order number: 245264-005
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the pentium ? ii i processor may contain design defects or errors known as errata which may cause the product to deviate from published specifcations. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2000 *third-party brands and names are the property of their respective owners.
datasheet 3 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz contents 1.0 introduction................................................................................................................ ......... 7 1.1 terminology........................................................................................................... 8 1.1.1 package and processor terminology ...................................................... 8 1.1.2 processor naming convention.................................................................9 1.2 related documents.............................................................................................10 2.0 electrical specifications................................................................................................... .11 2.1 processor system bus and v ref ........................................................................11 2.2 clock control and low power states..................................................................12 2.2.1 normal statestate 1 ...........................................................................13 2.2.2 autohalt powerdown statestate 2...................................................13 2.2.3 stop-grant statestate 3 .....................................................................13 2.2.4 halt/grant snoop statestate 4 ........................................................14 2.2.5 sleep statestate 5..............................................................................14 2.2.6 deep sleep statestate 6 ....................................................................14 2.2.7 clock control..........................................................................................15 2.3 power and ground pins ......................................................................................15 2.3.1 phase lock loop (pll) power...............................................................16 2.4 decoupling guidelines .......................................................................................16 2.4.1 processor vcc core decoupling............................................................16 2.4.2 processor system bus agtl+ decoupling............................................16 2.5 processor system bus clock and processor clocking .......................................17 2.5.1 mixing processors of differrent frequencies .........................................17 2.6 voltage identification ...........................................................................................17 2.7 processor system bus unused pins...................................................................19 2.8 processor system bus signal groups ................................................................19 2.8.1 asynchronous vs. synchronous for system bus signals .......................20 2.8.2 system bus frequency select signals (bsel[1:0]) ...............................21 2.9 test access port (tap) connection....................................................................22 2.10 maximum ratings................................................................................................22 2.11 processor dc specifications...............................................................................23 2.12 agtl+ system bus specifications .....................................................................27 2.13 system bus ac specifications ............................................................................27 2.13.1 i/o buffer model .....................................................................................28 3.0 signal quality specifications ............................................................................................36 3.1 bclk and picclk signal quality specifications and measurement guidelines ....................................................................................36 3.2 agtl+ signal quality specifications and measurement guidelines ..................37 3.3 agtl+ signal quality specifications and measurement guidelines ..................38 3.3.1 overshoot/undershoot guidelines .........................................................38 3.3.2 overshoot/undershoot magnitude .........................................................39 3.3.3 overshoot/undershoot pulse duration...................................................39 3.3.4 activity factor .........................................................................................39 3.3.5 reading overshoot/undershoot specification tables............................40 3.3.6 determining if a system meets the overshoot/undershoot specifications .........................................................................................41
pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 4 datasheet 3.4 non-agtl+ signal quality specifications and measurement guidelines........... 43 3.4.1 overshoot/undershoot guidelines ......................................................... 44 3.4.2 ringback specification........................................................................... 44 3.4.3 settling limit guideline .......................................................................... 44 4.0 thermal specifications and design considerations......................................................... 45 4.1 thermal specifications........................................................................................ 45 4.1.1 thermal diode........................................................................................ 46 5.0 mechanical specifications............................................................................................... 48 5.1 fc-pga mechanical specifications .................................................................... 48 5.2 processor markings ............................................................................................ 50 5.3 processor signal listing...................................................................................... 50 6.0 boxed processor specifications....................................................................................... 62 6.1 mechanical specifications................................................................................... 62 6.1.1 boxed processor thermal cooling solution dimensions....................... 62 6.1.2 boxed processor heatsink weight......................................................... 64 6.1.3 boxed processor thermal cooling solution clip ................................... 64 6.2 boxed processor requirements ......................................................................... 65 6.2.1 fan heatsink power supply ................................................................... 65 6.3 thermal specifications........................................................................................ 66 6.3.1 boxed processor cooling requirements ............................................... 66 7.0 processor signal description ........................................................................................... 68 7.1 alphabetical signals reference .......................................................................... 68 7.2 signal summaries ............................................................................................... 75
datasheet 5 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz list of figures 1 second level (l2) cache implementation ........................................................... 7 2 agtl+ bus topology in a uniprocessor configuration ......................................12 3 agtl+ bus topology in a dual-processor configuration ...................................12 4 stop clock state machine ...................................................................................12 5 processor vcc cmos package routing ................................................................16 6 bsel[1:0] example for a 100/133 mhz or 100 mhz only system design .........21 7 bclk, picclk, and tck generic clock waveform...........................................33 8 system bus valid delay timings ........................................................................33 9 system bus setup and hold timings..................................................................33 10 system bus reset and configuration timings....................................................34 11 power-on reset and configuration timings.......................................................34 12 test timings (tap connection) ..........................................................................35 13 test reset timings .............................................................................................35 14 bclk, picclk generic clock waveform at the processor pins........................37 15 low to high agtl+ receiver ringback tolerance.............................................38 16 maximum acceptable agtl+ overshoot/undershoot waveform .......................43 17 non-agtl+ overshoot/undershoot, settling limit, and ringback 1 ..................43 18 processor functional die layout ........................................................................46 19 package dimensions...........................................................................................48 20 top side processor markings .............................................................................50 21 intel ? pentium ? iii processor pinout ...................................................................51 22 conceptual boxed intel ? pentium ? iii processor for the pga370 socket ..........62 23 side view of space requirements for the boxed processor ..............................63 24 side view of space requirements for the boxed processor ..............................63 25 dimensions of mechanical step feature in heatsink base.................................64 26 clip keepout requirements for boxed intel ? pentium ? iii processors ...............64 27 boxed processor fan heatsink power cable connector description.................65 28 motherboard power header placement relative to the boxed intel ? pentium ? iii processor ..............................................................................66 29 thermal airspace requirement for all boxed intel ? pentium ? iii processor fan heatsinks in the pga370 socket................................................67
pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 6 datasheet list of tables 1 processor identification......................................................................................... 9 2 voltage identification definition........................................................................... 18 3 system bus signal groups ................................................................................ 20 4 frequency select truth table for bsel[1:0] ...................................................... 21 5 absolute maximum ratings ................................................................................ 22 6 voltage and current specifications .................................................................... 24 7 agtl+ signal groups dc specifications ........................................................... 26 8 non-agtl+ signal group dc specifications ..................................................... 26 9 processor agtl+ bus specifications ................................................................ 27 10 system bus ac specifications (clock) ............................................................... 28 11 valid system bus to core frequency ratios ..................................................... 29 12 system bus ac specifications (agtl+ signal group) ....................................... 30 13 system bus ac specifications (cmos signal group) ....................................... 30 14 system bus ac specifications (reset conditions) ............................................ 31 15 system bus ac specifications (apic clock and apic i/o) ................................ 31 16 system bus ac specifications (tap connection) .............................................. 32 17 bclk/picclk signal quality specifications for simulation at the processor pins ......................................................................................... 36 18 agtl+ signal groups ringback tolerance specifications at the processor pins ......................................................................................... 37 19 example platform information............................................................................. 40 20 100 mhz agtl+ signal group overshoot/undershoot tolerance at processor pins ................................................................................................ 41 21 133 mhz agtl+ signal group overshoot/undershoot tolerance ..................... 42 22 33 mhz cmos signal group overshoot/undershoot tolerance at processor pins ................................................................................................ 42 23 signal ringback specifications for non-agtl+ signal simulation at the processor pins ....................................................................... 44 24 intel? pentium? iii processor for the pga370 socket thermal specification.......................................................................................... 45 25 thermal diode parameters ................................................................................. 47 26 thermal diode interface...................................................................................... 47 27 intel? pentium? iii processor package dimensions .......................................... 49 28 processor die loading parameters .................................................................... 49 29 signal listing in order by signal name .............................................................. 52 30 signal listing in order by pin number ................................................................ 57 31 boxed processor fan heatsink spatial dimensions........................................... 63 32 fan heatsink power and signal specifications................................................... 65 33 signal description ............................................................................................... 68 34 output signals..................................................................................................... 75 35 input signals ....................................................................................................... 76 36 input/output signals (single driver).................................................................... 77 37 input/output signals (multiple driver) ................................................................. 77
datasheet 7 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 1.0 introduction the intel ? pentium ? iii processor for the pga370 socket is the next member of the p6 family, in the intel ia-32 processor line and hereafter will be referred to as the pentium iii processor, or simply the processor. the processor uses the same core and offers the same performance as the intel ? pentium ? iii processor for the sc242 connector, but utilizes a new package technology called flip-chip pin grid array, or fc-pga. this package utilizes the same 370-pin zero insertion force socket (pga370) used by the intel ? celeron tm processor. thermal solutions are attached directly to the back of the processor core package without the use of a thermal plate or heat spreader. the pentium iii processor, like its predecessors in the p6 family of processors, implements a dynamic execution microarchitecturea unique combination of multiple branch prediction, data flow analysis, and speculative execution. this enables these processors to deliver higher performance than the intel pentium processor, while maintaining binary compatibility with all previous intel architecture processors. the processor also executes intel ? mmx tm technology instructions for enhanced media and communication performance just as its predecessor, the intel pentium iii processor. additionally, pentium iii processor executes streaming simd (single- instruction, multiple data) extensions for enhanced floating point and 3-d application performance. the concept of processor identification, via cpuid, is extended in the processor family with the addition of a processor serial number. refer to the intel ? processor serial number application note for more detailed information. the processor utilizes multiple low-power states such as autohalt, stop-grant, sleep, and deep sleep to conserve power during idle times. the processor includes an integrated on-die, 256 kb, 8-way set associative level-two (l2) cache. the l2 cache implements the new advanced transfer cache architecture with a 256-bit wide bus. the processor also includes a 16 kb level one (l1) instruction cache and 16 kb l1 data cache. these cache arrays run at the full speed of the processor core. as with the intel pentium iii processor for the sc242 connector, the pentium iii processor for the pga370 socket has a dedicated l2 cache bus, thus maintaining the dual independent bus architecture to deliver high bus bandwidth and performance (see figure 1 ). memory is cacheable for 64 gb of addressable memory space, allowing significant headroom for desktop systems. refer to the specification update document for this processor to determine the cacheability and cache configuration options for a specific processor. the specification update document can be requested at your nearest intel sales office. the processor utilizes the same multiprocessing system bus technology as the pentium ii processor. this allows for a higher level of performance for both uni-processor and two-way multiprocessor systems. the system bus uses a variant of gtl+ signaling technology called assisted gunning transceiver logic (agtl+) signaling technology. figure 1. second level (l2) cache implementation processor core tag l2 processor core l2 intel ? pentium ? iii secc2 processor intel ? pentium ? iii fc-pga processor
8 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 1.1 terminology in this document, a # symbol after a signal name refers to an active low signal. this means that a signal is in the active state (based on the name of the signal) when driven to a low level. for example, when flush# is low, a flush has been requested. when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the # symbol implies that the signal is inverted. for example, d[3:0] = hlhl refers to a hex a, and d[3:0]# = lhlh also refers to a hex a (h= high logic level, l= low logic level). the term system bus refers to the interface between the processor, system core logic (a.k.a. the chipset components), and other bus agents. 1.1.1 package and processor terminology the following terms are used often in this document and are explained here for clarification: ? pentium ? iii processor - the entire product including all internal components. ? pga370 socket - 370-pin zero insertion force (zif) socket which a fc-pga or ppga packaged processor plugs into. ? fc-pga - flip chip pin grid array. the package technology used on pentium iii processors for the pga370 socket. ? advanced transfer cache (atc) - new l2 cache architecture unique to the 0.18 micron pentium iii processors. atc consists of microarchitectural improvements that provide a higher data bandwidth interface into the processor core that is completely scaleable with the processor core frequency. ? keep-out zone - the area on or near a fc-pga packaged processor that system designs can not utilize. ? keep-in zone - the area of a fc-pga packaged processor that thermal solutions may utilize. ? olga - organic land grid array. the package technology for the core used in s.e.c.c. 2 processors that permits attachment of the heatsink directly to the die. ? ppga - plastic pin grid array. the package technology used for intel ? celeron tm processors that utilize the pga370 socket. ? processor - for this document, the term processor is the generic form of the pentium iii processor for the pga370 socket in the fc-pga package. ? processor core - the processors execution engine. ? s.e.c.c. - the processor package technology called single edge contact cartridge. used with intel ? pentium ? ii processors. ? s.e.c.c. 2 - the follow-on to s.e.c.c. processor package technology. this differs from its predecessor in that it has no extended thermal plate, thus reducing thermal resistance. used with intel ? pentium ? iii processors and latest versions of the intel ? pentium ? ii processor. ? sc242 - the 242-contact slot connector (previously referred to as slot 1 connector) that the s.e.c.c. and s.e.c.c. 2 plug into, just as the intel ? pentium ? pro processor uses socket 8. the cache and l2 cache are an industry designated names.
datasheet 9 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 1.1.2 processor naming convention a letter(s) is added to certain processors (e.g., 600eb mhz) when the core freqnency alone may not uniquely identify the processor. below is a summary of what each letter means as well as a table listing all the available pentium iii processors for the pga370 socket. b 133 mhz system bus frequency e processor with "advanced transfer cache" (cpuid 068xh and greater) notes: 1. refer to the pentium ? iii processor specification update for the exact cpuid for each processor. 2. atc = advanced transfer cache. atc is an l2 cache integrated on the same die as the processor core. with atc, the interface between the processor core and l2 cache is 256-bits wide, runs at the same frequency as the processor core and has enhanced buffering. 3. this item is currently not por. table 1. processor identification processor core frequency (mhz) system bus frequency (mhz) l2 cache size (kbytes) l2 cache type 2 cpuid 1 500e 500 100 256 atc 068xh 533eb 533 133 256 atc 068xh 550e 550 100 256 atc 068xh 600e 600 100 256 atc 068xh 600eb 600 133 256 atc 068xh 650 650 100 256 atc 068xh 667 667 133 256 atc 068xh 700 700 100 256 atc 068xh 733 733 133 256 atc 068xh 750 750 100 256 atc 068xh 800 800 mhz 100 256 atc 068xh 800eb 800 mhz 133 256 atc 068xh 850 850 mhz 100 256 atc 068xh 866 866 mhz 133 256 atc 068xh 933 933 mhz 133 256 atc 068xh
10 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 1.2 related documents the reader of this specification should also be familiar with material and concepts presented in the following documents 1,2 : note: 1. unless otherwise noted, this reference material can be found on the intel developers website located at http://developer.intel.com. 2. for a complete listing of intel ? pentium ? iii processor reference material, please refer to the intel developers website at http://developer.intel.com/design/pentium iii /. 3. this material is available through an intel field sales representative. document intel order number ap-485, intel ? processor identification and the cpuid instruction 241618 ap-585, pentium ? ii processor gtl+ guidelines 243330 ap-589, design for emi 243334 ap-905, pentium ? iii processor thermal design guidelines 245087 ap-907, pentium ? iii processor power distribution guidelines 245085 ap-909, intel ? processor serial number 245125 intel ? architecture software developer's manual 243193 volume i: basic architecture 243190 volume ii: instruction set reference 243191 volume iii: system programming guide 243192 p6 family of processors hardware developers manual 244001 ia-32 processors and related products 1999 databook 243565 pentium ? ii processor developers manual 243502 pentium ? iii processor datasheet 244452 pentium ? iii processor specification update 244453 intel ? celeron tm processor datasheet 243658 intel ? celeron tm processor specificiation update 243748 370-pin socket (pga370) design guidelines 244410 pga370 heat sink cooling in microatx chassis 245025 intel ? 810e chipset platform design guide 3 intel ? 820 chipset platform design guide 3 intel ? 840 chipset platform design guide 3 ck98 clock synthesizer/driver specification 3 intel ? 810e chipset clock synthesizer/driver specification 3 vrm 8.4 dc-dc converter design guidelines 3 pentium iii processor for the pga370 socket i/o buffer models, xtk/xns* format 3 pentium ? pro processor bios writers guide 3 extensions to the pentium ? pro processor bios writers guide 3 pentium iii thermal/mechanical solution functional guidelines 245241
datasheet 11 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.0 electrical specifications 2.1 processor system bus and v ref the pentium iii processor signals use a variation of the low voltage gunning transceiver logic (gtl) signaling technology. the intel ? pentium ? pro processor system bus specification is similar to the gtl specification, but was enhanced to provide larger noise margins and reduced ringing. the improvements are accomplished by increasing the termination voltage level and controlling the edge rates. this specification is different from the gtl specification, and is referred to as gtl+. for more information on gtl+ specifications, see the gtl+ buffer specification in the intel ? pentium ? ii processor developers manual . current p6 family processors vary from the intel pentium pro processor in their output buffer implementation. the buffers that drive the system bus signals on the intel ? celeron tm , pentium ii, and pentium iii processors are actively driven to v cc core for one clock cycle after the low to high transition to improve rise times. these signals should still be considered open-drain and require termination to a supply that provides the high signal level. because this specification is different from the standard gtl+ specification, it is referred to as agtl+, or assisted gtl+ in this and other documentation. agtl+ logic and gtl+ logic are compatible with each other and may both be used on the same system bus. for more information on agtl+ routing, see the appropriate platform design guide. agtl+ inputs use differential receivers which require a reference signal (v ref ). v ref is used by the receivers to determine if a signal is a logical 0 or a logical 1, and is supplied by the motherboard to the pga370 socket for the processor core. local v ref copies should also be generated on the motherboard for all other devices on the agtl+ system bus. termination (usually a resistor at each end of the signal trace) is used to pull the bus up to the high voltage level and to control reflections on the transmission line. the processor contains on-die termination resistors that provide termination for one end of the agtl+ bus, except for reset#. these specifications assume another resistor at the end of each signal trace to ensure adequate signal quality for the agtl+ signals and provide backwards compatibility for the intel celeron processor; see table 9 for the bus termination voltage specifications for agtl+. refer to the intel ? pentium ? ii processor developers manual for the agtl+ bus specification. solutions exist for single-ended termination as well, though this implementation changes system design and eliminate backwards compatibility for intel celeron processors in the ppga package. single-ended termination designs must still provide an agtl+ termination resistor on the motherboard for the reset# signal. figure 2 is a schematic representation of the agtl+ bus topology for the pentium iii processors in the pga370 socket. figure 3 is a schematic representation of the agtl+ bus topoplogy in a dual- processor configuration with pentium iii processors in the pga370 socket. the agtl+ bus depends on incident wave switching. therefore, timing calculations for agtl+ signals are based on flight time as opposed to capacitive deratings. analog signal simulation of the system bus including trace lengths is highly recommended when designing a system with a heavily loaded agtl+ bus, especially for systems using a single set of termination resistors (i.e., those on the processor die). such designs will not match the solution space allowed for by installation of termination resistors on the baseboard.
12 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.2 clock control and low power states processors allow the use of autohalt, stop-grant, sleep, and deep sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 4 for a visual representation of the processor low power states. figure 2. agtl+ bus topology in a uniprocessor configuration figure 3. agtl+ bus topology in a dual-processor configuration processor chipset processor chipset processor figure 4. stop clock state machine pcb757a 2. auto halt power down state bclk running. snoops and interrupts allowed. halt i ns t ruc ti on an d halt bus cycle generated init#, binit#, intr, smi#, reset# 1. normal state normal execution. stpclk# asserted stpclk# de-asserted 3. stop grant state bclk running. snoops and interrupts allowed. slp# asserted slp# de-asserted 5. sleep state bclk running. no snoops or interrupts allowed. bclk input stopped bclk input restarted 6. deep sleep state bclk stopped. no snoops or interrupts allowed. 4. halt/grant snoop state bclk running. service snoops to caches. snoop event occurs snoop event serviced snoop event occurs snoop event serviced stpclk# asserted stpclk# de-asserted and stop-grant state entered from autohalt , nmi
datasheet 13 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz for the processor to fully realize the low current consumption of the stop-grant, sleep and deep sleep states, a model specific register (msr) bit must be set. for the msr at 02ah (hex), bit 26 must be set to a 1 (this is the power on default setting) for the processor to stop all internal clocks during these modes. for more information, see the intel architecture software developers manual, volume 3: system programming guide . 2.2.1 normal statestate 1 this is the normal operating state for the processor. 2.2.2 autohalt powerdown statestate 2 autohalt is a low power state entered when the processor executes the halt instruction. the processor transitions to the normal state upon the occurrence of smi#, init#, or lint[1:0] (nmi, intr). reset# causes the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the autohalt power down state. see the intel architecture software developer's manual, volume iii: system programmer's guide for more information. flush# is serviced during the autohalt state, and the processor will return to the autohalt state. the system can generate a stpclk# while the processor is in the autohalt power down state. when the system deasserts the stpclk# interrupt, the processor returns execution to the halt state. 2.2.3 stop-grant statestate 3 the stop-grant state on the processor is entered when the stpclk# signal is asserted. since the agtl+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to v tt ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the system bus should be driven to the inactive state. binit# and flush# are not serviced during the stop-grant state. reset# causes the processor to immediately initialize itself, but the processor stays in stop-grant state. a transition back to the normal state occurs with the deassertion of the stpclk# signal. a transition to the halt/grant snoop state occurs when the processor detects a snoop on the system bus (see section 2.2.4 ). a transition to the sleep state (see section 2.2.5 ) occurs with the assertion of the slp# signal. while in stop-grant state, smi#, init#, and lint[1:0] are latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event is recognized and serviced upon return to the normal state.
14 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.2.4 halt/grant snoop statestate 4 the processor responds to snoop transactions on the system bus while in stop-grant state or in autohalt power down state. during a snoop transaction, the processor enters the halt/grant snoop state. the processor stays in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). after the snoop is serviced, the processor returns to the stop-grant state or autohalt power down state, as appropriate. 2.2.5 sleep statestate 5 the sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all internal clocks. the sleep state can only be entered from the stop-grant state. once in the stop-grant state, the slp# pin can be asserted, causing the processor to enter the sleep state. the slp# pin is not recognized in the normal or autohalt states. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp# or reset#) are allowed on the system bus while the processor is in sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering its lowest power state, the deep sleep state, by stopping the bclk input (see section 2.2.6 ). once in the sleep or deep sleep states, the slp# pin can be deasserted if another asynchronous system bus event occurs. the slp# pin has a minimum assertion of one bclk period. 2.2.6 deep sleep statestate 6 the deep sleep state is the lowest power state the processor can enter while maintaining context. the deep sleep state is entered by stopping the bclk input (after the sleep state was entered from the assertion of the slp# pin). the processor is in deep sleep state immediately after blck is stopped. it is recommended that the blck input be held low during the deep sleep state. stopping of the bclk input lowers the overall current consumption to leakage levels. to re-enter the sleep state, the blck input must be restarted. a period of 1 ms (to allow for pll stabilization) must occur before the processor can be considered to be in the sleep state. once in the sleep state, the slp# pin can be deasserted to re-enter the stop-grant state. while in deep sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals are allowed on the system bus while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior.
datasheet 15 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.2.7 clock control bclk provides the clock signal for the processor and on die l2 cache. during autohalt power down and stop-grant states, the processor will process a system bus snoop. the processor does not stop the clock to the l2 cache during autohalt power down or stop-grant states. entrance into the halt/grant snoop state allows the l2 cache to be snooped, similar to the normal state. when the processor is in sleep and deep sleep states, it does not respond to interrupts or snoop transactions. during the sleep state, the internal clock to the l2 cache is not stopped. during the deep sleep state, the internal clock to the l2 cache is stopped. the internal clock to the l2 cache is restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor has re-entered sleep state). picclk should not be removed during the autohalt power down or stop-grant states. picclk can be removed during the sleep or deep sleep states. when transitioning from the deep sleep state to the sleep state, picclk must be restarted with bclk. 2.3 power and ground pins the operating voltage of the pentium iii processor for the pga370 socket is the same for the core and the l2 cache; v cc core . there are four pins defined on the package for voltage identification (vid). these pins specify the voltage required by the processor core. these have been added to cleanly support voltage specification variations on current and future processors. for clean on-chip power and voltage reference distribution, the pentium iii processors in the fc-pga package have 75 v cc core , 8 v ref , 15 v tt , and 77 v ss (ground) inputs. v cc core inputs supply the processor core, including the on-die l2 cache. v tt inputs (1.5v) are used to provide an agtl+ termination voltage to the processor, and the v ref inputs are used as the agtl+ reference voltage for the processor. note that not all v tt inputs must be connected to the v tt supply. refer to section 5.3 for more details. on the motherboard, all v cc core pins must be connected to a voltage island (an island is a portion of a power plane that has been divided, or an entire plane). in addition, the motherboard must implement the v tt pins as a voltage island or large trace. similarly, all gnd pins must be connected to a system ground plane. three additional power related pins exist on a processors utilizing the pga370 socket. they are v cc 1.5 , v cc 2.5 and v cc cmos . the v cc cmos pin provides the cmos voltage for the pull-up resistors required on the system platform. a 2.5v source must be provided to the v cc 2.5 pin and a 1.5v source must be provided to the v cc 1.5 pin. the source for v cc 1.5 must be the same as the one supplying v tt . the processor routes the compatible cmos voltage source (1.5v or 2.5v) through the package and out to the v cc cmos output pin. processors based on 0.25 micron technology (e.g., the intel celeron processor) utilize 2.5v cmos buffers. processors based on 0.18 micron technology (e.g., the pentium iii processor for the pga370 socket) utilize 1.5v cmos buffers. the signal v core det can be used by hardware on the motherboard to detect which cmos voltage the processor requires. a v core det connected to v ss within the processor indicates a 1.5v requirement on v cc cmos . refer to figure 5 . each power signal must meet the specifications stated in table 6 on page 24 .
16 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.3.1 phase lock loop (pll) power it is highly critical that phase lock loop power delivery to the processor meets intels requirements. a low pass filter is required for power delivery to pins pll1 and pll2. this serves as an isolated, decoupled power source for the internal pll. please refer to the phase lock loop power section in the appropriate platform design guide for the recommended filter specifications. 2.4 decoupling guidelines due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. the fluctuations can cause voltages on power planes to sag below their nominal values if bulk decoupling is not adequate. care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in table 6 . failure to do so can result in timing violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a voltage overshoot). unlike sc242 based designs, motherboards utilizing the pga370 socket must provide high frequency decoupling capacitors on all power planes for the processor. 2.4.1 processor v cc core decoupling the regulator for the v cc core input must be capable of delivering the di cc core /dt (defined in table 6 ) while maintaining the required tolerances (also defined in table 6 ). failure to meet these specifications can result in timing violations (during v cc core sag) or a reduced lifetime of the component (during v cc core overshoot). 2.4.2 processor system bus agtl+ decoupling the processor requires both high frequency and bulk decoupling on the system motherboard for proper agtl+ bus operation. see the agtl+ buffer specification in the intel ? pentium ? ii processor developer's manual for more information. also, refer to the appropriate platform design guide for recommended capacitor component placement. figure 5. processor v cc cmos package routing intel ? pentium ? iii processor 0.1 uf 2.5v supply 2.5v 1.5v supply 1.5v vcc cmos *ich or other logic cmos pullups cmos signals note: *ensure this logic is compatible with 1.5v signal levels of the intel ? pentium ? iii processor for the pga370 socket.
datasheet 17 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.5 processor system bus clock and processor clocking the bclk input directly controls the operating speed of the system bus interface. all agtl+ system bus timing parameters are specified with respect to the rising edge of the bclk input. see the p6 family of processors hardware developer's manual for further details. 2.5.1 mixing processors of differrent frequencies in two-way mp (multi-processor) systems, mixing processors of different internal clock frequencies is not supported and has not been validated. pentium iii processors do not support a variable multiplier ratio; therefore, adjusting the ratio setting to a common clock frequency is not valid. however, mixing processors of the same frequency but of different steppings is supported. details on support for mixed steppings is provided in the pentium ? iii processor specification update . note: not all pentium iii processors for the pga370 socket are validated for use in dual processor (dp) systems. refer to the pentium ? iii processor specification update to determine which processors are dp capable. 2.6 voltage identification there are four voltage identification pins on the pga370 socket. these pins can be used to support automatic selection of v cc core voltages. these pins are not signals, but are either an open circuit or a short circuit to v ss on the processor. the combination of opens and shorts defines the voltage required by the processor core. the vid pins are needed to cleanly support voltage specification variations on current and future processors. vid[3:0] are defined in table 2 . a 1 in this table refers to an open pin and a 0 refers to a short to ground. the voltage regulator or vrm must supply the voltage that is requested or disable itself. to ensure a system is ready for current and future processors, the range of values in bold in table 2 should be supported. a smaller range will risk the ability of the system to migrate to a higher performance processor and/or maintain compatibility with current processors.
18 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. 0 = processor pin connected to v ss . 2. 1 = open on processor; may be pulled up to ttl v ih on baseboard. 3. to ensure a system is ready for the intel ? pentium ? iii and intel ? celeron tm processors, the values in bold in table 2 should be supported. note that the 1111 (all opens) id can be used to detect the absence of a processor core in a given socket as long as the power supply used does not affect these lines. detection logic and pull-ups should not affect vid inputs at the power source (see section 7.0 ). the vid pins should be pulled up to a ttl-compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the vid[3:0] signals. the power source chosen must be guaranteed to be stable whenever the supply to the voltage regulator is stable. this will prevent the possibility of the processor supply going above the specified v cc core in the event of a failure in the supply for the vid lines. in the case of a dc-to- dc converter, this can be accomplished by using the input voltage to the converter for the vid line pull-ups. a resistor of greater than or equal to 10 k w may be used to connect the vid signals to the converter input. note that no changes have been made to the physical connector or pin definitions between the intel-enabled vrm 8.2 and vrm 8.4 specifications. intel requires that designs utilize vrm 8.4 specifications to meet the pentium iii processor requirements . table 2. voltage identification definition 1, 2 vid3 vid2 vid1 vid0 vcc core 1111 1.30 1110 1.35 1101 1.40 1100 1.45 1011 1.50 1010 1.55 1001 1.60 3 1000 1.65 3 0111 1.70 3 0110 1.75 3 0101 1.80 3 0100 1.85 3 0011 1.90 3 0010 1.95 3 0001 2.00 3 0000 2.05 3 1111 no core
datasheet 19 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.7 processor system bus unused pins all reserved pins must remain unconnected unless specifically noted. connection of these pins to v cc core , v ref , v ss , v tt , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. see section 5.3 for a pin listing of the processor and the location of each reserved pin. picclk must be driven with a valid clock input and the picd[1:0] signals must be pulled-up to v cc cmos even when the apic will not be used. a separate pull-up resistor must be provided for each picd signal. for reliable operation, always connect unused inputs or bidirectional signals to their deasserted signal level. the pull-up or pull-down resistor values are system dependent and should be chosen such that the logic high (v ih ) and logic low (v il ) requirements are met. see table 8 for dc specifications of non-agtl+ signals. unused agtl+ inputs must be properly terminated to v tt on pga370 socket motherboards which support the intel celeron and the pentium iii processors. for designs that intend to only support the pentium iii processor, unused agtl+ inputs will be terminated by the processors on- die termination resistors and thus do not need to be terminated on the motherboard. however, reset# must always be terminated on the motherboard as the pentium iii processor for the pga370 socket does not provide on-die termination of this agtl+ input. for unused cmos inputs, active low signals should be connected through a pull-up resistor to v cc cmos and meet v ih requirements. unused active high cmos inputs should be connected through a pull-down resistor to ground (v ss ) and meet v il requirements. unused cmos outputs can be left unconnected. a resistor must be used when tying bidirectional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testability. 2.8 processor system bus signal groups to simplify the following discussion, the processor system bus signals have been combined into groups by buffer type. all p6 family processor system bus outputs are open drain and require a high-level source provided termination resistors. however, the pentium iii processor for the pga370 socket includes on-die termination. motherboard designs that also support intel celeron processors in the ppga package will need to provide agtl+ termination on the system motherboard as well. platform designs that support dual processor configurations will need to provide agtl+ termination, via a termination package, in any socket not populated with a processor. agtl+ input signals have differential input buffers which use v ref as a reference signal. agtl+ output signals require termination to 1.5 v. in this document, the term agtl+ input refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, agtl+ output refers to the agtl+ output group as well as the agtl+ i/o group when driving. the pwrgood, bclk, and picclk inputs can each be driven from ground to 2.5 v. other cmos inputs (a20m#, ignne#, init#, lint0/intr, lint1/nmi, preq#, smi, slp#, and stpclk#) are only 1.5 v tolerant and must be pulled up to v cc cmos . the cmos, apic, and tap outputs are open drain and must be pulled high to v cc cmos . this ensures correct operation for current intel pentium iii and intel celeron processors. the groups and the signals contained within each group are shown in table 3 . refer to section 7.0 for a description of these signals.
20 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. see section 7.0 for information on the these signals. 2. the br0# pin is the only breq# signal that is bidirectional. see section 7.0 for more information. the internal breq# signals are mapped onto the br[1:0]# pins after the agent id is determined. 3. these signals are specified for vcc cmos (1.5 v for the pentium iii processor) operation. 4. these signals are 2.5 v tolerant. 5. v cc core is the power supply for the processor core and is described in section 2.6 . vid[3:0] is described in section 2.6 . v tt is used to terminate the system bus and generate v ref on the motherboard. v ss is system ground. v cc 1.5 , v cc 2.5 , vcc cmos are described in section 2.3 . bsel[1:0] is described in section 2.8.2 and section 7.0 . all other signals are described in section 7.0 . 6. reset# must always be terminated to v tt on the motherboard, on-die termination is not provided for this signal. 7. this signal is not supported by all processors. refer to the pentium ? iii processor specification update for a complete listing of processors that support this pin. 8. this signal is used to control the value of the processor on-die termination resistance. refer to the platform design guide for the recommended pulldown resistor value. 2.8.1 asynchronous vs. synchronous for system bus signals all agtl+ signals are synchronous to bclk. all of the cmos, clock, apic, and tap signals can be applied asynchronously to bclk. all apic signals are synchronous to picclk. all tap signals are synchronous to tck. table 3. system bus signal groups 1 group name signals agtl+ input bpri#, br1# 7 , defer#, reset# 6 , rs[2:0]#, rsp#, trdy# agtl+ output prdy# agtl+ i/o a[35:3]#, ads#, aerr#, ap[1:0]#, berr#, binit#, bnr#, bp[3:2]#, bpm[1:0]#, br0# 2 , d[63:0]#, dbsy#, dep[7:0]#, drdy#, hit#, hitm#, lock#, req[4:0]#, rp# cmos input 3 a20m#, flush#, ignne#, init#, lint0/intr, lint1/nmi, preq#, slp#, smi#, stpclk# cmos input 4 pwrgood cmos output 3 ferr#, ierr#, thermtrip# system bus clock 4 bclk apic clock 4 picclk apic i/o 3 picd[1:0] tap input 3 tck, tdi, tms, trst# tap output 3 tdo power/other 5 bsel[1:0], clkref, cpupres#, edgctrl, pll[2:1], reset2#, slewctrl, thermdn, thermdp, rttctrl 8 , v core det , vid[3:0], v cc 1.5 , v cc 2.5 , v cc cmos , v cc core , v ref , v ss , v tt , reserved
datasheet 21 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.8.2 system bus frequency select signals (bsel[1:0]) these signals are used to select the system bus frequency. table 2.9 defines the possible combinations of the signals and the frequency associated with each combination. the frequency is determined by the processor(s), chipset, and clock synthesizer. all system bus agents must operate at the same frequency. the pentium iii processor for the pga370 socket operates at 100 mhz or 133 mhz system bus frequency; 66 mhz system bus operation is not supported . individual processors will only operate at their specified front side bus (fsb) frequency, either 100 mhz or 133 mhz, not both. on motherboards that support operation at either 100 mhz or 133 mhz, the bsel1 signal must be pulled up to a logic high by a resistor located on the motherboard and provided as a frequency selection signal to the clock driver/synthesizer. this signal can also be incorporated into reset# logic on the motherboard if only 133 mhz operation is supported (thus forcing the reset# signal to remain active as long as the bsel1 signal is low. the bsel0 signal will float from the processor and should be pulled up to a logic high by a resistor located on the motherboard. the bsel0 signal can be incorporated into reset# logic on the motherboard if 66 mhz operation is unsupported, as demonstrated in figure 6 . refer to the appropriate clock synthesizer design guidelines and platform design guide for more details on the bus frequency select signals. in a 2-way mp system design, these bsel[1:0] signals must connect the pins of both processors. notes: 1. some clock drivers may require a series resistor on their bsel1 input. 2. some chipsets may connect to the bsel[1:0] signals and require a series resistor. see the appropriate platform design guide for implementation details. figure 6. bsel[1:0] example for a 100/133 mhz or 100 mhz only system design processor bsel0 bsel1 chipset clock driver 1 k w 1 k w 3.3v 3.3v 10 k w note 1 10 k w note 2 10 k w note 2 table 4. frequency select truth table for bsel[1:0] bsel1 bsel0 frequency 0 0 66 mhz (unsupported) 0 1 100 mhz 10 reserved 1 1 133 mhz
22 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.9 test access port (tap) connection due to the voltage levels supported by other components in the test access port (tap) logic, it is recommended that the processor be the first in the tap chain and followed by any other components within the system. a translation buffer should be used to connect the rest of the chain unless one of the other components is capable of accepting a 1.5v input. similar considerations must be made for tck, tms, and trst# signals. in a two-way mp system design, be cautious when including an empty pga370 socket in the scan chain. all sockets in the scan chain must have a processor installed to complete the chain or the system must support a method to bypass the empty socket; pga370 termination packages should not connect tdi to tdo in order to avoid placing the tdo pull-up resistor in parallel. 2.10 maximum ratings table 5 contains processor stress ratings only. functional operation at the absolute maximum and minimum is not implied nor guaranteed. the processor should not receive a clock while subjected to these conditions. functional operating conditions are given in the ac and dc tables in section 2.11 through section 2.13 . extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. notes: 1. input voltage can never exceed v ss + 2.18 volts. 2. input voltage can never go below v tt - 2.18 volts. 3. parameter applies to cmos (except bclk, picclk, and pwrgood), apic, and tap bus signal groups only. 4. parameter applies to cmos signals bclk, picclk, and pwrgood only. table 5. absolute maximum ratings symbol parameter min max unit notes t storage processor storage temperature C40 85 c v cc core and v tt processor core voltage and termination supply voltage with respect to v ss C0.5 2.1 v v in agtl agtl+ buffer input voltage v tt - 2.18 2.18 v 1, 2 v in cmos 1.5 cmos buffer dc input voltage with respect to v ss v tt - 2.18 2.18 v 1, 2, 3 v in cmos 2.5 cmos buffer dc input voltage with respect to v ss -0.58 3.18 v 4 i vid max vid pin current 5 ma i cpupres# max cpupres# pin current 5 ma
datasheet 23 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.11 processor dc specifications the processor dc specifications in this section are defined at the pga370 socket pins (bottom side of the motherboard). see section 7.0 for the processor signal descriptions and section 5.3 for the signal listings. most of the signals on the processor system bus are in the agtl+ signal group. these signals are specified to be terminated to 1.5v. the dc specifications for these signals are listed in table 7 on page 26 . to allow connection with other devices, the clock, cmos, apic, and tap signals are designed to interface at non-agtl+ levels. the dc specifications for these pins are listed in table 8 on page 26 . table 6 through table 9 list the dc specifications for the pentium iii processor for the pga370 socket. specifications are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. care should be taken to read all notes associated with each parameter.
24 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz t able 6 . v oltage a nd curr e nt spe c if i cations 1, 2 (sheet 1 of 2) s ymbol p arameter core f r eq min t yp m ax unit no t es v cc c o re v cc for proce s sor core 500 e m hz 533e b mhz 550 e m hz 600 e m hz 600e b mhz 65 0 m hz 667 b m hz 70 0 m hz 733 b m hz 75 0 m hz 80 0 m hz 800e b mhz 85 0 m hz 86 6 m hz 93 3 m hz 1.60 1.65 1.60 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 1.65 v 3, 4 3, 4 3, 4, 19 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4, v tt , v cc 1 . 5 s tat i c a gtl + bus termination v o l tage 1.4 5 5 1.50 1.5 4 5 v 1.5 3% , 5, 16 v tt , v cc 1 . 5 t r ansient agtl + b u s termination v o l tage 1.3 6 5 1.50 1.6 3 5 v 1.5 9% , 5 v r e f a gtl+ i n p ut refe r ence v o l tage -2% 2/3 v t t +2% v 2%, 7 v clk r ef cl k ref i nput referen c e voltage 1.1 6 9 1.25 1.3 3 1 v 6.5%, 15 ba s eboard v cc c o re t oleran c e, s t atic p roce s sor core voltage stat i c tolerance leve l at the p ga37 0 soc k et pins C0.080 0.0 4 0 v 6 ba s eboard v cc c o re t oleran c e, t ran s i e n t p roce s sor core voltage transient tolera n ce level at th e p ga37 0 soc k et pins C0.130 C0. 1 10 0.0 8 0 0.0 8 0 v 6 18 i cc c o re i cc for proce s sor core 500 e m hz 533e b mhz 550 e m hz 600 e m hz 600e b mhz 65 0 m hz 667 b m hz 70 0 m hz 733 b m hz 75 0 m hz 80 0 m hz 800e b mhz 85 0 m hz 86 6 m hz 93 3 m hz 10.0 10.6 1 1 . 0 12.0 12.0 13.0 13.3 14.0 14.6 15.0 16.0 16.0 16.2 16.3 17.7 a 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 3, 8, 9 i cc c m os i cc for v cc c m os 250 ma i cl k ref cl k ref voltage s u pp l y c urrent 60 a i v tt t e rminat i on voltage s u pp l y c urrent 2.7 a 10 i s g n t i cc s top - g r ant for pro c essor c ore 2.5 a 8, 1 1 i s l p i cc slee p for p roces s or c o re 2.5 a 8
datasheet 25 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all specifications in this table apply only to the pentium iii processor. for motherboard compatibility with the intel ? celeron tm processor, see the intel ? celeron tm processor datasheet . 3. vcc core and icc core supply the processor core and the on-die l2 cache. 4. use the typical voltage specification with the tolerance specifications to provide correct voltage regulation to the processor. 5. v tt and vcc 1.5 must be held to 1.5v 9% while the agtl+ bus is active. it is required that v tt and vcc 1.5 be held to 1.5v 3% while the processor system bus is static (idle condition). the 3% range is the required design target; 9% will come from the transient noise added. this is measured at the pga370 socket pins on the bottom side of the baseboard. 6. these are the tolerance requirements, across a 20 mhz frequency bandwidth, measured at the processor socket pin on the soldered-side of the motherboard. v cc core must return to within the static voltage specification within 100 m s after a transient event; see the vrm 8.4 dc-dc converter design guidelines for further details. 7. v ref should be generated from v tt by a voltage divider of 1% resistors or 1% matched resistors. refer to the intel ? pentium ? ii processor developers manual for more details on v ref . 8. maximum i cc is measured at v cc typical voltage and under a maximum signal loading conditions. 9. voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of vcc core (vcc core_typ ). in this case, the maximum current level for the regulator, icc core_reg , can be reduced from the specified maximum current icc core _max and is calculated by the equation: icc core_reg = icc core_max (vcc core_typ - vcc core_static_tolerance ) / vcc core_typ 10.the current specified is the current required for a single processor. a similar amount of current is drawn through the termination resistors on the opposite end of the agtl+ bus, unless single-ended termination is used (see section 2.1 ). 11.the current specified is also for autohalt state. 12.maximum values are specified by design/characterization at nominal vcc core . 13.based on simulation and averaged over the duration of any change in current. use to compute the maximum inductance tolerable and reaction time of the voltage regulator. this parameter is not tested. 14.dicc/dt specifications are measured and specified at the pga370 socket pins. 15.clkref must be held to 1.25v 6.5%. this tolerance accounts for a 5% power supply and 1% resistor divider tolerance. it is recommended that the motherboard generate the clkref reference from either the 2.5v or 3.3v supply. v tt should not be used due to risk of agtl+ switching noise coupling to this analog reference. 16.static voltage regulation includes: dc output initial voltage set point adjust, output ripple and noise, output load ranges specified in the tables above. 17.fmb - flexible motherboard recommendation 18.this specification applies to pga370 processors operating at frequencies of 933mhz or higher. 19.vcc=1.65v for cb0 core stepping (cpuid 0683h); vcc=1.60v for ca2 core stepping (cpuid 0681h). i dslp i cc deep sleep for processor core 2.2 a di cc core /dt power supply current slew rate 240 a/s 12, 13, 14 di v tt /dt termination current slew rate 8a/s 12, 13, see table 9 table 6. voltage and current specifications 1, 2 (sheet 2 of 2) symbol parameter core freq min typ max unit notes
26 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. unless otherwise noted, all specifications in this table apply to pentium iii processors at all frequencies. 2. all inputs, outputs, and i/o pins must comply with the signal quality specifications in section 3.0 . 3. minimum and maximum v tt are given in table 9 on page 27 . 4. (0 v in 1.5 v +3%) and (0 v out 1.5v+3%). 5. refer to the processor i/o buffer models for i/v characteristics. 6. steady state input voltage must not be above v ss + 1.65v or below v tt - 1.65v. notes: 1. unless otherwise noted, all specifications in this table apply to pentum iii processors at all frequencies. 2. parameter measured at 9 ma (for use with ttl inputs). 3. (0 v in 2.5v +5%). 4. (0 v out 2.5v +5%). 5. for bclk specifications, refer to table 17 on page 36 . 6. (0 v in 1.5v +3%). 7. (0 v out 1.5v +3%). 8. applies to non-agtl+ signals bclk, picclk, and pwrgood. 9. applies to non-agtl+ signals except bclk, picclk, and pwrgood. table 7. agtl+ signal groups dc specifications 1, symbol parameter min max unit notes v il input low voltage C0.150 v ref - 0.200 v 6 v ih input high voltage v ref + 0.200 v tt v 2, 3, 6 ron buffer on resistance 16.67 w 5 i l leakage current for inputs, outputs, and i/o 100 a 4 table 8. non-agtl+ signal group dc specifications 1 symbol parameter min max unit notes v il 1.5 input low voltage C0.150 v ref - 0.200 v 9 v il 2.5 input low voltage -0.58 0.700 v 5, 8 v ih 1.5 input high voltage v ref + 0.200 v tt v6, 9 v ih 2.5 input high voltage 2.000 3.18 v 5, 8 v ol output low voltage 0.400 v 2 v oh output high voltage v tt v 7, 9, all outputs are open-drain i ol output low current 9 ma i li input leakage current 100 a 3, 6 i lo output leakage current 100 a 4, 7
datasheet 27 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 2.12 agtl+ system bus specifications it is recommended that the agtl+ bus be routed in a daisy-chain fashion with termination resistors to v tt . these termination resistors are placed electrically between the ends of the signal traces and the v tt voltage supply and generally are chosen to approximate the system platform impedance. the valid high and low levels are determined by the input buffers using a reference voltage called v ref . refer to the appropriate platform design guide for more information table 9 below lists the nominal specification for the agtl+ termination voltage (v tt ). the agtl+ reference voltage (v ref ) is generated on the system motherboard and should be set to 2/3 v tt for the processor and other agtl+ logic. it is important that the baseboard impedance be specified and held to a 15% tolerance, and that the intrinsic trace capacitance for the agtl+ signal group traces is known and well-controlled. for more details on the agtl+ buffer specification, see the intel ? pentium ? ii processor developer's manual and ap-585, intel ? pentium ? ii processor agtl+ guidelines . notes: 1. unless otherwise noted, all specifications in this table apply to pentium iii processors at all frequencies. 2. pentium iii processors for the pga370 socket contain agtl+ termination resistors on the processor die, except for the reset# input. 3. v tt and vcc 1.5 must be held to 1.5v 9%. it is required that v tt and vcc 1.5 be held to 1.5v 3% while the processor system bus is idle (static condition). this is measured at the pga370 socket pins on the bottom side of the baseboard. 4. the value of the on-die r tt is determined by the resistor value measured by the rttctrl signal pin. see section 7.0 for more details on the rttctrl signal. refer to the recommendation guidelines for the specific chipset/processor combination. 5. v ref is generated on the motherboard and should be 2/3 v tt 2% nominally. insure that there is adequate v ref decoupling on the motherboard. 2.13 system bus ac specifications the processor system bus timings specified in this section are defined at the socket pins on the bottom of the motherboard. unless otherwise specified, timings are tested at the processor pins during manufacturing. timings at the processor pins are specified by design characterization. see section 7.0 for the processor signal definitions. table 10 through table 16 list the ac specifications associated with the processor system bus. these specifications are broken into the following categories: table 10 contains the system bus clock specifications, table 12 contains the agtl+ specifications, table 13 contains the cmos signal group specifications, table 14 contains timings for the reset conditions, table 15 and covers apic bus timing, and table 16 covers tap timing. all processor system bus ac specifications for the agtl+ signal group are relative to the rising edge of the bclk input. all agtl+ timings are referenced to v ref for both 0 and 1 logic levels unless otherwise specified. table 9. processor agtl+ bus specifications 1, 2 symbol parameter min typ max units notes v tt bus termination voltage 1.50 v 3 on-die r tt termination resistor 40 130 w 4 v ref bus reference voltage 0.950 2/3 v tt 1.05 v 5
28 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz the timings specified in this section should be used in conjunction with the i/o buffer models provided by intel. these i/o buffer models, which include package information, are available for the pentium iii processor in the fc-pga package in viewlogic* xtk/xns* model format (formerly known as quad format) as the pentium iii processor for the pga370 socket i/o buffer models, xtk/xns format (electronic format). agtl+ layout guidelines are also available in the appropriate platform design guide. care should be taken to read all notes associated with a particular timing parameter. 2.13.1 i/o buffer model an electronic copy of the i/o buffer model for the agtl+ and cmos signals is available at intels developers website (http://developer.intel.com). the model is for use in single processor designs and assumes the presence of motherboard r tt values as described in table 9 on page 27 . 1. unless otherwise noted, all specifications in this table apply to pentium iii processors at all frequencies. 2. all ac timings for the agtl+ signals are referenced to the bclk rising edge at 1.25v at the processor pin. all agtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00v at the processor pins. 3. n/a 4. the internal core clock frequency is derived from the processor system bus clock. the system bus clock to core clock ratio is determined during initialization. individual processors will only operate at their specified system bus frequency, either 100 mhz or 133 mhz, not both. table 11 shows the supported ratios for each processor. 5. the bclk period allows a +0.5 ns tolerance for clock driver variation. see the appropriate clock synthesizer/ driver specification for details. 6. due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pf. this should be measured on the rising edges of adjacent bclks crossing 1.25v at the processor pin . the jitter present must be accounted for as a component of bclk timing skew between devices. 7. the clock drivers closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by the clock driver. the C20 db attenuation point, as measured into a 10 to 20 pf load, should be less than 500 khz. this specification may be ensured by design characterization and/or measured with a spectrum analyzer. see the appropriate clock synthesizer/driver specification for details 8. bclk rise time is measure between 0.5vC2.0v. bclk fall time is measured between 2.0vC0.5v. 9. bclk high time is measured as the period of time above 2.0v. bclk low time is measured as the period of time below 0.5v 10.this specification applies to pentium iii processors operating at a system bus frequency of 100 mhz. 11.this specification applies to pentium iii processors operating at a system bus frequency of 133 mhz. 12.not 100% tested. specified by design characterization as a clock driver requirement. table 10. system bus ac specifications (clock) 1, 2, 3 t# parameter min nom max unit figure notes system bus frequency 100.00 133.33 mhz 4 4 t1: bclk period 10.0 7.5 ns 7 4, 5, 10 4, 5, 11 t2: bclk period stability 250 250 ps 6, 7, 10 6, 7, 11 t3: bclk high time 2.5 1.4 ns 7 9, 10 9, 11 t4: bclk low time 2.4 1.4 ns 7 9, 10 9, 11 t5: bclk rise time 0.4 1.6 ns 7 8, 12 t6: bclk fall time 0.4 1.6 ns 7 8, 12
datasheet 29 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz note: 1. contact your local intel representative for the latest information on processor frequencies and/or frequency multipliers. 2. while other bus ratios are defined, operation at frequencies other than those listed are not supported by the pentium iii processor. 3. individual processors will only operate at their specified system bus frequency. either 100 mhz or 133 mhz, not both. table 11. valid system bus to core frequency ratios 1, 2, 3 processor core frequency (mhz) bclk frequency (mhz) frequency multiplier l2 cache (mhz) 500e 500 100 5 500 533eb 533 133 4 533 550e 550 100 11/2 550 600e 600 100 6 600 600eb 600 133 9/2 600 650 650 100 13/2 650 667 667 133 5 667 700 700 100 7 700 733 733 133 11/2 733 750 750 100 15/2 750 800 800.00 100.00 8 800.00 800eb 800.00 133.33 6 800.00 850 850.00 100.00 17/2 850.00 866 866.00 133.33 13/2 866.00 933 933.00 133.33 7 933.00
30 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. unless otherwise noted, all specifications in this table apply to pentium iii processors at all frequencies. 2. these specifications are tested during manufacturing. 3. all ac timings for the agtl+ signals are referenced to the bclk rising edge at 1.25v at the processor pin. all agtl+ signal timings (compatibility signals, etc.) are referenced at 1.00v at the processor pins. 4. valid delay timings for these signals are specified into 50 w to 1.5v, v ref at 1.0 v 2% and with 56 w on-die r tt . 5. a minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of trdy#. 6. reset# can be asserted (active) asynchronously, but must be deasserted synchronously. for 2-way mp systems, reset# should be synchrounous. 7. specification is for a minimum 0.40 v swing from v ref - 200 mv to v ref + 200 mv. this assumes an edge rate of 0.3v/ns. 8. specification is for a maximum 1.0 v swing from v tt - 1v to v tt . this assumes an edge rate of 3v/ns. 9. this should be measured after v cc core , v tt , vcc cmos , and bclk become stable. 10.this specification applies to the pentium iii processor running at 100 mhz system bus frequency. 11.this specification applies to the pentium iii processor running at 133 mhz system bus frequency. 12.breq signals at 133 mhz system bus observe a 1.2 ns minimum setup time. notes: 1. unless otherwise noted, all specifications in this table apply to pentium iii processors at all frequencies 2. these specifications are tested during manufacturing. 3. these signals may be driven asynchronously. 4. all cmos outputs shall be asserted for at least 2 bclks. 5. when driven inactive or after v cc core , v tt , v cc cmos , and bclk become stable. table 12. system bus ac specifications (agtl+ signal group) 1, 2, 3 t# parameter min max unit figure notes t7: agtl+ output valid delay 0.40 3.25 ns 8 4, 10, 11 t8: agtl+ input setup time 1.20 0.95 ns ns 9 9 5, 6, 7, 10 5, 6, 7, 11, 12 t9: agtl+ input hold time 1.00 ns 9 8, 10 t10: reset# pulse width 1.00 ms 10 6, 9, 10 table 13. system bus ac specifications (cmos signal group) 1, 2, 3, 4 t# parameter min max unit figure notes t14: cmos input pulse width, except pwrgood 2bclks 8 active and inactive states t15: pwrgood inactive pulse width 10 bclks 8 , 11 5
datasheet 31 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. unless otherwise noted, all specifications in this table apply to all pentium iii processor frequencies. notes: 1. unless otherwise noted, all specifications in this table apply to pentium iii processors at all frequencies. 2. these specifications are tested during manufacturing. 3. all ac timings for the apic i/o signals are referenced to the picclk rising edge at 1.25 v at the processor pins. all apic i/o signal timings are referenced at 0.75 v at the processor pins. 4. referenced to picclk rising edge. 5. for open drain signals, valid delay is synonymous with float delay. 6. valid delay timings for these signals are specified into 150 w load pulled up to 1.5 v. table 14. system bus ac specifications (reset conditions) 1 t# parameter min max unit figure notes t16: reset configuration signals (a[14:5]#, br0#, init#) setup time 4bclks 10 before deassertion of reset# t17: reset configuration signals (a[14:5]#, br0#, init#) hold time 220bclks 10 after clock that deasserts reset# table 15. system bus ac specifications (apic clock and apic i/o) 1, 2, 3 t# parameter min max unit figure notes t21: picclk frequency 2.0 33.3 mhz t22: picclk period 30.0 500.0 ns 7 t23: picclk high time 10.5 ns 7 @ > 1.7v t24: picclk low time 10.5 ns 7 @ < 0.7v t25: picclk rise time 0.25 3.0 ns 7 (0.7v - 1.7v) t26: picclk fall time 0.25 3.0 ns 7 (1.7v - 0.7v) t27: picd[1:0] setup time 5.0 ns 9 4 t28: picd[1:0] hold time 2.5 ns 9 4 t29a: picd[1:0] valid delay (rising edge) 1.5 8.7 ns 7 , 8 4, 5, 6 t29b: picd[1:0] valid delay (falling edge) 1.5 12.0 ns 7 , 8 4, 5, 6
32 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. unless otherwise noted, all specifications in this table apply to all pentium iii processors frequencies. 2. all ac timings for the tap signals are referenced to the tck rising edge at 0.75 v at the processor pins. all tap signal timings (tms, tdi, etc.) are referenced at 0.75 v at the processor pins. 3. these specifications are tested during manufacturing, unless otherwise noted. 4. 1 ns can be added to the maximum tck rise and fall times for every 1 mhz below 16.667 mhz. 5. referenced to tck rising edge. 6. referenced to tck falling edge. 7. valid delay timing for this signal is specified to 1.5 v. 8. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo, and tms). these timings correspond to the response of these signals due to tap operations. 9. during debug port operation, use the normal specified timings rather than the tap signal timings. 10.not 100% tested. specified by design characterization. note: for figure 7 through figure 13 , the following apply: 1. figure 7 through figure 13 are to be used in conjunction with table 10 through table 16 . 2. all ac timings for the agtl+ signals at the processor pins are referenced to the bclk rising edge at 1.25 v. all agtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor pins. 3. all ac timings for the apic i/o signals at the processor pins are referenced to the picclk rising edge at 1.25 v. all apic i/o signal timings are referenced at 0.75 v at the processor pins. 4. all ac timings for the tap signals at the processor pins are referenced to the tck rising edge at 0.75 v. all tap signal timings (tms, tdi, etc.) are referenced at 0.75 v at the processor pins. table 16. system bus ac specifications (tap connection) 1, 2, 3 t# parameter min max unit figure notes t30: tck frequency 16.667 mhz t31: tck period 60.0 ns 7 t32: tck high time 25.0 ns 7 v ref + 0.200v, 10 t33: tck low time 25.0 ns 7 v ref - 0.200v, 10 t34: tck rise time 5.0 ns 7 (v ref - 0.200v) - (v ref + 0.200v), 4, 10 t35: tck fall time 5.0 ns 7 (v ref + 0.200v) - (v ref - 0.200v), 4, 10 t36: trst# pulse width 40.0 ns 13 asynchronous, 10 t37: tdi, tms setup time 5.0 ns 12 5 t38: tdi, tms hold time 14.0 ns 12 5 t39: tdo valid delay 1.0 10.0 ns 12 6, 7 t40: tdo float delay 25.0 ns 12 6, 7, 10 t41: all non-test outputs valid delay 2.0 25.0 ns 12 6, 8, 9 t42: all non-test inputs setup time 25.0 ns 12 6, 8, 9, 10 t43: all non-test inputs setup time 5.0 ns 12 5, 8, 9 t44: all non-test inputs hold time 13.0 ns 12 5, 8, 9
datasheet 33 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz figure 7. bclk, picclk, and tck generic clock waveform figure 8. system bus valid delay timings figure 9. system bus setup and hold timings t r = t5, t25, t34, (rise time) t f = t6, t26, t35, (fall time) t h = t3, t23, t32, (high time) t l = t4, t24, t33, (low time) t p = t1, t22, t31 (bclk, tck, picclk period) v1 = bclk is referenced to 0.5v. tck is referenced to v ref - 200mv. picclk is referenced to 0.7v. v2 = bclk is referenced to 2.0v. tck is referenced to vref - 200mv. picclk is referenced to 1.7v. v3 = bclk and picclk are referenced to 1.25v. tck is referenced to v ref . v2 v3 v1 t r t p t f t h t l clk clk signal valid valid tx v tx tpw tx = t7, t11, t29a, t29b (valid delay) tpw = t14, t15 (pulse width) v = 1.0v for agtl+ signal group; 0.75v for cmos, apic and tap signal groups clk signal valid ts v th ts = t8, t12, t27 (setup time) th = t9, t13, t28 (hold time) v = 1.0v for agtl+ signal group; 0.75v for apic and tap signal groups
34 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz figure 10. system bus reset and configuration timings figure 11. power-on reset and configuration timings t y safe valid t z valid t v t w t x t u t t bclk reset# configuration (a20m#, ignne#, lint[1:0]) configuration (a[14:5]#, br0#, flush#, int#) t t = t9 (agtl+ input hold time) t u = t8 (agtl+ input setup time) t v = t10 (reset# pulse width) t w = t16 (reset configuration signals (a[14:5]#, br0#, flush#, init#) setup time) t x = t17 (reset configuration signals (a[14:5]#, br0#, flush#, init#) hold time) t20 (reset configuration signals (a20m#, ignne#, lint[1:0]) hold time) ty = t19 (reset configuration signals (a20m#, ignne#, lint[1:0]) delay time) tz = t18 (reset configuration signals (a20m#, ignne#, lint[1:0]) setup time) t a valid ratio t c t b pwrgood reset# configuration (a20m#, ignne#, intr, nmi) t a = t15 (pwrgood inactive pulse) t b = t10 (reset# pulse width) t c = t20 (reset configuration signals (a20m#, ignne#, lint[1:0]) hold time) bclk v il, max v ih, min vcc core , v tt , v ref
datasheet 35 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz figure 12. test timings (tap connection) figure 13. test reset timings t r = t43 (all non-test inputs setup time) t s = t44 (all non-test inputs hold time) t u = t40 (tdo float delay) t v = t37 (tdi, tms setup time) t w = t38 (tdi, tms hold time) t x = t39 (tdo valid delay) t y = t41 (all non-test outputs valid delay) t z = t42 (all non-test outputs float time) t v t w t r t s t u t z t x t y tck tdi, tms input signal tdo output signal t q trst# t q = t36 (trst# pulse width) 1.25v
36 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 3.0 signal quality specifications signals driven on the processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. specifications are provided for simulation at the processor pins. meeting the specifications at the processor pins in table 17 , table 18 , and table 23 ensures that signal quality effects will not adversely affect processor operation. 3.1 bclk and picclk signal quality specifications and measurement guidelines table 17 describes the signal quality specifications at the processor pins for the processor system bus clock (bclk) and apic clock (picclk) signals. figure 14 describes the signal quality waveform for the system bus clock at the processor pins. notes: 1. unless otherwise noted, all specifications in this table apply to all pentium iii processors frequencies. 2. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk/picclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. this specification is an absolute value. table 17. bclk/picclk signal quality specifications for simulation at the processor pins 1 t# parameter min nom max unit figure notes v1: bclk v il 0.500 v 14 v1: picclk v il 0.700 v 14 v2: bclk v ih 2.000 v 14 v2 picclk v ih 2.000 v 14 v3: v in absolute voltage range C0.58 3.18 v 14 v4: bclk rising edge ringback 2.000 v 14 2 v4: picclk rising edge ringback 2.000 v 14 2 v5: bclk falling edge ringback 0.500 v 14 2 v5: picclk falling edge ringback 0.700 v 14 2
datasheet 37 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 3.2 agtl+ signal quality specifications and measurement guidelines many scenarios have been simulated to generate a set of agtl+ layout guidelines which are available in the appropriate platform design guide. refer to the intel ? pentium ? ii processor developer's manual (order number 243502) for the agtl+ buffer specification. table 18 provides the agtl+ signal quality specifications for the processor for use in simulating signal quality at the processor pins. the pentium iii processor for the pga370 socket maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in table 20 through table 22 . figure 15 shows the agtl+ ringback tolerance and figure 16 shows the overshoot/undershoot waveform. notes: 1. unless otherwise noted, all specifications in this table apply to all pentium iii processors frequencies. 2. specifications are for the edge rate of 0.3 - 0.8v/ns. see figure 15 for the generic waveform. 3. all values specified by design characterization. 4. please see table 20 for maximum allowable overshoot. 5. ringback between v ref + 100 mv and v ref + 200 mv or v ref - 200 mv and v ref - 100 mvs requires the flight time measurements to be adjusted as described in the intel agtl+ specifications ( intel ? pentium ? ii developers manual ). ringback below v ref + 100 mv or above v ref - 100 mv is not supported. 6. intel recommends simulations not exceed a ringback value of v ref 200 mv to allow margin for other sources of system noise. 7. a negative value for r indicates that the amplitude of ringback is above v ref . (i.e., f = -100 mv specifies the signal cannot ringback below v ref + 100 mv). 8. f and r : are measured relative to v ref . a : is measured relative to v ref + 200 mv. figure 14. bclk, picclk generic clock waveform at the processor pins v2 v1 v3 v3 v4 v5 table 18. agtl+ signal groups ringback tolerance specifications at the processor pins 1, 2, 3 t# parameter min unit figure notes a : overshoot 100 mv 15 4, 8 t : minimum time at high 0.50 ns 15 r : amplitude of ringback 200 mv 15 5, 6, 7, 8 f : final settling voltage 200 mv 15 8 d : duration of squarewave ringback n/a ns 15
38 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 3.3 agtl+ signal quality specifications and measurement guidelines 3.3.1 overshoot/undershoot guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below v ss . the overshoot guideline limits transitions beyond v cc or v ss due to the fast signal edge rates. the processor can be damaged by repeated overshoot events on 1.5 v or 2.5 v tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction and the activity factor (af). permanent damage to the processor is the likely result of excessive overshoot/undershoot. violating the overshoot/undershoot guideline will also make satisfying the ringback specification difficult. when performing simulations to determine impact of overshoot and overshoot, esd diodes must be properly characterized. esd protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. esd diodes modeled within intel i/o buffer models do not clamp undershoot or overshoot and will yield correct simulation results. if other i/o buffer models are being used to characterize the pentium iii processor performance, care must be taken to ensure that esd models do not clamp extreme voltage levels. intel i/o buffer models also contain i/o capacitance characterization. therefore, removing the esd diodes from an i/o buffer model will impact results and may yield excessive overshoot/undershoot. figure 15. low to high agtl+ receiver ringback tolerance ibk tl 0.7v clk ref clock time v start v ref - 0.2 v ref v ref + 0.2 note: high to low case is analogous t a d r f
datasheet 39 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 3.3.2 overshoot/undershoot magnitude magnitude describes the maximum potential difference between a signal and its voltage reference level, v ss (overshoot) and v tt (undershoot). while overshoot can be measured relative to v ss using one probe (probe to signal and gnd lead to v ss ), undershoot must be measured relative to v tt . this could be acomplished by simultaneously measuring the v tt plane while measuring the signal undershoot. todays oscilloscopes can easily calculate the true undershoot waveform. the true undershoot waveform can also be obtained with the following oscilloscope data file analysis: converted undershoot waveform = v tt - signal_measured note: the converted undershoot waveform appears as a positive (overshoot) signal. note: overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact must be determined independently. after the true waveform conversion, the undershoot/overshoot specifications shown in table 20 through table 22 can be applied to the converted undershoot waveform using the same magnitude and pulse duration specifications used with an overshoot waveform. overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in table 20 through table 22 . these specifications must not be violated at any time regardless of bus activity or system state. within these specifications are threshold levels that define different allowed pulse durations. provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications (2.18v), the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications. 3.3.3 overshoot/undershoot pulse duration pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (vos_ref = 1.635v). the total time could encompass several oscillations above the reference voltage. multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. note: oscillations below the reference voltage can not be substracted from the total overshoot/ undershoot pulse duration. note: multiple overshoot/undershoot events occurring within the same clock cycle must be considered together as one event. using the worst case overshoot/undershoot magnitude, sum together the individual pulse duraitons to determine the total overshoot/undershoot pulse duration for that total event. 3.3.4 activity factor activity factor (af) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. since the highest frequency of assertion of an agtl+ or a cmos signal is every other clock, an af = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. thus, an af = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. the specifications provided in table 20 through table 22 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/undershoot events of that magnitude only. a platform with an overshoot/undershoot
40 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz that just meets the pulse duration for a specific magnitude where the af < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if af = 1, then the event occurs at all times and no other events can occur). note: activity factor for agtl+ signals is referenced to bclk frequency. note: activity factor for cmos signals is referenced to picclk frequency. 3.3.5 reading overshoot/undershoot specification tables the overshoot/undershoot specification for the pentium iii processor for the pga370 socket is not a simple single value. instead, many factors are needed to determine what the over/undershoot specification is. in addition to the magnitude of the overshoot, the following parameters must also be known: the junction temperature the processor will be operating at, the width of the overshoot (as measured above 1.635v) and the activity factor (af). to determine the allowed overshoot for a particular overshoot event, the following must be done: 1. determine the signal group that particular signal falls into. if the signal is an agtl+ signal operating with a 100 mhz system bus, use table 20 (100mhz agtl+ signal group). if the signal is an agtl+ signal operating with a 133mhz system bus, use table 21 (133 mhz agtl+ signal group). if the signal is a cmos signal, use table 22 (33 mhz cmos signal group). 2. determine the maximum junction temperature (tj) for the range of processors that the system will support (80 o c or 85 o c). 3. determine the magnitude of the overshoot (relative to v ss ) 4. determine the activity factor (how often does this overshoot occur?) 5. from the appropriate specification table, read off the maximum pulse duration (in ns) allowed. 6. compare the specified maximum pulse duration to the signal being measured. if the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. the above procedure is similar for undershoots after the undershoot waveform has been converted to look like an overshoot. undershoot events must be analyzed separately from overshoot events as they are mutually exclusive. below is an example showing how the maximum pulse duration is determined for a given waveform. notes: 1. corresponding maximum puse duration specification - 2.4 ns 2. pulse duration (measured) - 2.0 ns given the above parameters, and using table 21 (85 o c/af = 0.1 column) the maximum allowed pulse duration is 2.4 ns. since the measure pulse duration is 2.0 ns, this particular overshoot event passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/ undershoot events meet the specifications. table 19. example platform information required information maximum platform support notes fsb signal group 133 mhz agtl+ max tj 85 c overshoot magnitude 2.13v measured value activity factor (af) 0.1 measured overshoot occurs on average every 20 clocks
datasheet 41 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 3.3.6 determining if a system meets the overshoot/undershoot specifications the overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. however most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, af and magnitude). while each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail. a guideline to ensure a system passes the overshoot and undershoot specifications is shown below. it is important to meet these guidelines; otherwise, contact your intrel field representative. 1. insure no signal (cmos or agtl+) ever exceed the 1.635v or 2. if only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot specifications in the following tables or 3. if multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the af = 1 specifications. if all of these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where af=1), then the system passes. the following notes apply to table 20 through table 22 . notes: 1. overshoot/undershoot magnitude = 2.18v is an absolute value and should never be exceeded 2. overshoot is measured relative to v ss . 3. undershoot is measured relative to v tt 4. overshoot/undershoot pulse duration is measured relative to 1.635v. 5. rinbacks below v tt can not be subtracted from overshoots/undershoots 6. lesser undershoot does not allocate longer or larger overshoot 7. oem's are encouraged to follow intel provided layout guidelines. consult the layout guidelines provided in the specific platform design guide. 8. all values specified by design characterization 1. bclk period is 10 ns. 2. measurements taken at the processor socket pins on the solder-side of the motherboard. table 20. 100 mhz agtl+ signal group overshoot/undershoot tolerance at processor pins 1,2 overshoot/ undershoot magnitude maximum pulse duration at tj = 80 c (ns) maximum pulse duration at tj = 85 c (ns) af = 0.01 af = 0.1 af = 1 af = 0.01 af = 0.1 af = 1 2.18 v 20 2.53 0.25 18.6 1.86 0.18 2.13 v 20 4.93 0.49 20 3.2 0.32 2.08 v 20 9.1 0.91 20 6.1 0.6 2.03 v 20 16.6 1.67 20 11.4 1.1 1.98 v 20 20 3.0 20 20 2 1.93 v 20 20 5.5 20 20 6.6 1.88 v 202010202020
42 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 1. bclk period is 7.5 ns. 2. measurements taken at the processor socket pins on the solder-side of the motherboard. notes: 1. picclk period is 30 ns. 2. measurements taken at the processor socket pins on the solder-side of the motherboard. table 21. 133 mhz agtl+ signal group overshoot/undershoot tolerance 1, 2 overshoot/undershoot magnitude maximum pulse duration at tj = 80 c (ns) maximum pulse duration at tj = 85 c (ns) af = 0.01 af = 0.1 af = 1 af = 0.01 af = 0.1 af = 1 2.18 v 15 1.9 0.19 14 1.4 0.14 2.13 v 15 3.7 0.37 15 2.4 0.24 2.08 v 15 6.8 0.68 15 4.6 0.46 2.03 v 15 12.5 1.25 15 8.6 0.84 1.98 v 15 15 2.28 15 15 1.5 1.93 v 15 15 4.1 15 15 5 1.88 v 15 15 7.5 15 15 15 table 22. 33 mhz cmos signal group overshoot/undershoot tolerance at processor pins 1, 2 overshoot/ undershoot magnitude maximum pulse duration at tj = 80 c (ns) maximum pulse duration at tj = 85 c (ns) af = 0.01 af = 0.1 af = 1 af = 0.01 af = 0.1 af = 1 2.18 v 60 7.6 0.76 56 5.6 0.56 2.13 v 60 14.8 1.48 60 9.6 0.96 2.08 v 60 27.2 2.7 60 18.4 1.8 2.03 v 60 50 5 60 33 3.3 1.98 v 60 60 9.1 60 60 6 1.93 v 60 60 16.4 60 60 20 1.88 v 606030606060
datasheet 43 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 3.4 non-agtl+ signal quality specifications and measurement guidelines there are three signal quality parameters defined for non-agtl+ signals: overshoot/undershoot, ringback, and settling limit. all three signal quality parameters are shown in figure 17 for the non- agtl+ signal group. notes: 1. v hi = 1.5v for all non-agtl+ signals except for bclk, picclk, and pwrgood. v hi = 2.5 v for bclk, picclk, and pwrgood. bclk and picclk signal quality is detailed in section 3.1 . figure 16. maximum acceptable agtl+ overshoot/undershoot waveform vss undershoot magnitude = v tt - signal overshoot magnitude = signal - vss v tt 2.18v 2.08v 1.98v 1.88v 1.635v max overshoot magnitude time dependent overshoot converted undershoot waveform undershoot magnitude time dependent undershoot figure 17. non-agtl+ overshoot/undershoot, settling limit, and ringback 1 undershoot overshoot settling limit settling limit rising-edge ringback falling-edge ringback v lo v ss time v hi
44 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 3.4.1 overshoot/undershoot guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below v ss . the overshoot guideline limits transitions beyond v cc or v ss due to the fast signal edge rates (see figure 17 for non-agtl+ signals). the processor can be damaged by repeated overshoot events on 1.5 v or 2.5 v tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). permanent damage to the processor is the likely result of excessive overshoot/undershoot. violating the overshoot/undershoot guideline will also make satisfying the ringback specification difficult. the overshoot/undershoot guideline is 0.3 v and assumes the absence of diodes on the input. these guidelines should be verified in simulations without the on- chip esd protection diodes present because the diodes will begin clamping the 1.5 v and 2.5 v tolerant signals beginning at approximately 0.7 v above the appropriate supply and 0.7 v below v ss . if signals are not reaching the clamping voltage, this will not be an issue. a system should not rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult. note: the undershoot guideline limits transitions exactly as described for the atgl+ signals. see figure 16 . 3.4.2 ringback specification ringback refers to the amount of reflection seen after a signal has switched. the ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value. see figure 17 for an illustration of ringback. excessive ringback can cause false signal detection or extend the propagation delay. the ringback specification applies to the input pin of each receiving agent. violations of the signal ringback specification are not allowed under any circumstances for non-agtl+ signals. ringback can be simulated with or without the input protection diodes that can be added to the input buffer model. however, signals that reach the clamping voltage should be evaluated further. see table 23 for the signal ringback specifications for non-agtl+ signals for simulations at the processor pins. notes: 1. unless otherwise noted, all specifications in this table apply to all pentium iii processor frequencies. 2. non-agtl+ signals except pwrgood. 3.4.3 settling limit guideline settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. the amount allowed is 10% of the total signal swing (v hi C v lo ) above and below its final value. a signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. simulations to verify settling limit may be done either with or without the input protection diodes present. violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions. table 23. signal ringback specifications for non-agtl+ signal simulation at the processor pins 1 input signal group transition maximum ringback (with input diodes present) unit figure non-agtl+ signals 2 0 ? 1 vref + 0.200 v 17 non-agtl+ signals 2 1 ? 0 vref - 0.200 v 17 pwrgood 0 ? 1 2.00 v 17
datasheet 45 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 4.0 thermal specifications and design considerations this chapter provides needed data for designing a thermal solution. however, for the correct thermal measuring processes, refer to ap-905, intel ? pentium ? iii processor thermal design guidelines (order number 245087). the pentium iii processor uses flip chip pin grid array packaging technology and has a junction temperature (t junction ) specified. 4.1 thermal specifications table 24 provides the thermal design power dissipation and maximum temperatures for the pentium iii processor for the pga370 socket. systems should design for the highest possible processor power, even if a processor with a lower thermal dissipation is planned. a thermal solution should be designed to ensure the junction temperature never exceeds these specifications. notes: 1. thermal design power (tdp) represents the maximum amount of power the thermal solution is required to dissipate. the thermal solution should be designed to dissipate the tdp power without exceeding the maximum tjunction specification. 2. tdp does not represent the power delivery and voltage regulation requirements for the processor. refer to table 6 for voltage regulation and electrical specifications. 3. t junctionoffset is the worst-case difference between the thermal reading from the on-die thermal diode and the hottest location on the processors core. 4. t junctionoffset values do not include any thermal diode kit measurement error. diode kit measurement error must be added to the t junctionoffset value from the table, as outlined in the pentium ? iii processor thermal design guidelines . intel has characterized the use of the analog devices ad1021 diode measurement kit and found its measurement error to be 1 c. table 24. intel ? pentium ? iii processor for the pga370 socket thermal specifications processor processor core frequency (mhz) l2 cache size (kbytes) processor thermal design power 1,2 (w) power density 5 (w/cm 2 ) maximum t junction (c) t junction offset 3,4,6 (c) 500e 500 256 13.2 18.2 85 1.9 533eb 533 256 14.0 19.3 85 2.0 550e 550 256 14.5 20.0 85 2.1 600e 600 256 15.8 21.8 82 2.3 600eb 600 256 15.8 21.8 82 2.3 650 650 256 17.0 23.4 82 2.5 667 667 256 17.5 24.1 82 2.5 700 700 256 18.3 25.2 80 2.7 733 733 256 19.1 26.3 80 2.8 750 750 256 19.5 26.9 80 2.8 800 800 256 20.8 28.7 80 3.0 800eb 800 256 20.8 28.7 80 3.0 850 850 256 22.5 31.0 80 3.3 866 866 256 22.9 31.5 80 3.3 933 933 256 24.5 33.8 75 3.6
46 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 5. power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the die area over which the power is generated. power for these processors is generated from the core area shown in figure 18 . 6. t junction offset values do not include any thermal diode kit measurement error. diode kit measurement error must be added to the t junction offset value from the table, as outlined in the intel ? pentium ? iii processor thermal metrology for cpuid-068h family processors (order number: 245301). intel has characterized the use of the analog devices ad1021 diode measurement kit and found its measurement error to be 1 c. figure 18 is a block diagram of the pentium iii processor die layout. the layout differentiates the processor core from the cache die area. in effect, the thermal design power indentified in table 24 is dissipated entirely from the processor core area. thermal solution designs should compensate for this smaller heat flux area and not assume that the power is uniformly distributed across the entire die area. 4.1.1 thermal diode the pentium iii processor for the pga370 socket incorporates an on-die diode that may be used to monitor the die temperature (junction temperature). a thermal sensor located on the motherboard, or a stand-alone measurement kit, may monitor the die temperature of the processor for thermal management or instrumentation purposes. table 25 and table 26 provide the diode parameter and interface specifications. note: the reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die. this is due to inaccuracies in the thermal sensor, on- die temperature gradients between the location of the thermal diode and the hottest location on the die at a given point in time, and time based variations in the die temperature measurement. time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the t junction temperature can change. figure 18. processor functional die layout die area (1.046 cm 2 ) core area (0.726 cm 2 ) cache area (0.320 cm 2 )
datasheet 47 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. characterized at 100 c with a forward bias current of 5 - 300 m a. 3. the ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: i fw =is(e^ ((vd*q)/(nkt)) - 1), where is = saturation current, q = electronic charge, vd = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). 4. not 100% tested. specified by design characterization. table 25. thermal diode parameters 1 symbol parameter min typ max unit notes i fw forward bias current 5 300 a 1 n diode ideality factor 1.0057 1.0080 1.0125 2, 3, 4 table 26. thermal diode interface pin name pga370 socket pin # pin description thermdp al31 diode anode (p_junction) thermdn al29 diode cathode (n_junction)
48 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 5.0 mechanical specifications the pentium iii processor uses a fc-pga package technology. mechanical specifications for the processor are given in this section. see section 1.1.1 for a complete terminology listing. the processor utilizes a pga370 socket for installation into the motherboard. details on the socket are available in the 370-pin socket (pga370) design guidelines . note: for figure 19 , the following apply: 1. unless otherwise specified, the following drawings are dimensioned in inches. 2. all dimensions provided with tolerances are guaranteed to be met for all normal production product. 3. figures and drawings labeled as reference dimensions are provided for informational purposes only. reference dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. reference dimensions are not checked as part of the processor manufacturing. unless noted as such, dimensions in parentheses without tolerances are reference dimensions. 4. drawings are not to scale. 5.1 fc-pga mechanical specifications the following figure with package dimensions is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin-side capacitors will be located on the processor. table 27 includes the measurements for these dimensions in both inches and millimeters. figure 19. package dimensions
datasheet 49 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz notes: 1. capacitors will be placed on the pin-side of the fc-pga package in the area defined by g1, g2, and g3. this area is a keepout zone for motherboard designers. the bare processor die has mechanical load limits that should not be exceeded during heat sink assembly, mechanical stress testing, or standard drop and shipping conditions. the heatsink attach solution must not induce permanent stress into the processor substrate with the exception of a uniform load to maintain the heatsink to the processor thermal interface. the package dynamic and static loading parameters are listed in table 28 . for table 28 , the following apply: 1. it is not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions. 2. parameters assume uniformly applied loads notes: 1. this specification applies to a uniform and a non-uniform load. 2. this is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface table 27. intel ? pentium ? iii processor package dimensions symbol millimeters inches minimum maximum notes minimum maximum notes a1 0.787 0.889 0.031d 0.035 a2 1.000 1.200 0.039 0.047 b1 11.226 11.329 0.442 0.446 b2 9.296 9.398 0.366 0.370 c1 23.495 max 0.925 max c2 21.590 max 0.850 max d 49.428 49.632 1.946 1.954 d1 45.466 45.974 1.790 1.810 g1 0.000 17.780 0 0.700 g2 0.000 17.780 0 0.700 g3 0.000 0.889 0 0.035 h 2.540 nominal 0.100 nominal l 3.048 3.302 0.120 0.130 f p 0.431 0.483 pin diameter 0.017 0.019 pin tp 0.508 diameteric true position (pin-to-pin) 0.020 diameteric true position (pin-to-pin) table 28. processor die loading parameters parameter dynamic (max) 1 static (max) 2 unit silicon die surface 200 50 lbf silicon die edge 100 12 lbf
50 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 5.2 processor markings the following figure exemplifies the processor top-side markings and it is provided to aid in the identification of an pentium iii processor for the pga370 socket. table 27 lists the measurements for the package dimensions. 5.3 processor signal listing table 29 and table 30 provide the processor pin definitions. the signal locations on the pga370 socket are to be used for signal routing, simulation, and component placement on the baseboard. figure 21 provides a pin-side view of the pentium iii processor pin-out. the following notes apply to table 29 and table 30 : notes: 1. these pins are required for backwards compatibility with other intel processors. they are not used by the pentium iii processor. refer to the appropriate platform design guide and section 7.1 for implementation details. 2. reset# signal must be connected to pins ah4 and x4 for backwards compatibility. refer to the appropriate platform design guide and section 7.1 for implementation details. if backwards compatibility is not required, then reset2# (x4) should be connected to gnd. 3. vcc 1.5 v must be supplied by the same voltage source supplying the v tt pins. 4. these v tt pins must be left unconnected (n/c) for backwards compatibility with intel ? celeron? processors (cpuid 066xh). for designs which do not support the intel celeron processors (cpuid 066xh), and for compatibility with future processors, these v tt pins should be connected to the v tt plane. refer to the appropriate platform design guide and section 7.1 for implementation details. for dual processor designs, these pins must be connected to v tt . 5. this pin is required for backwards compatibility. if backwards compatibility is not required, this pin may be left connected to v cc core . refer to the appropriate platform design guide for implementation details. 6. previously, pga370 designs defined this pin as a gnd. it is now reserved and must be left unconnected (n/c). 7. previously, pga370 socket designs defined this pin as a gnd. it is now clkref. 8. for uniprocessor designs, this pin is not used and it is defined as reserved. refer to the peniutm ? iii processor specification update for a complete listing of processors that support dp operation. figure 20. top side processor markings dynamic production mark example rb80526py550266 ffffffff-0001 sssss fpo # - s/n s-spec# pentium iii logo malay intel ? i (m) (c) 99 static mark ink printed at substrate supplier country of origin dynamic laser mark swatch product code
datasheet 51 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz figure 21. intel ? pentium ? iii processor pinout vss vcc vss d35 d29 d33 d26 d28 d21 d23 d25 vss vcc vss d31 vcc d43 vcc vss d34 d38 vcc vss d39 d36 vcc d37 d44 vcc vcc d32 d22 rsv d27 vss d42 d45 d49 vss vcc d63 vref1 vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss rsv vtt d62 slew ctrl dep6 dep4 vref0 bpm1 bp3 d41 d52 vss vcc vss vcc vss vcc vss vcc vss vcc d40 d59 d55 d54 d58 d50 d56 dep5 dep1 dep0 bpm0 cpupres vcc vss vcc vss vcc vss vcc vss vcc vss vcc binit d51 d47 d48 d57 d46 d53 d60 d61 dep7 dep7 dep3 dep2 prdy vss bp2 vtt rsv vcc vss vcc picclk picd0 preq vcc vcc vss rsv picd1 lint1 vcc vss lint0 rsv rsv rsv vss vcc vss rsv rsv rsv vcc vss vcc vtt rtt ctrl vtt vss vcc vss pll2 vtt vtt vcc vss vcc clkref vcc vss vcc vss v_2.5 vtt vtt vcc vss vcc v_cmos vss ferr rsp vcc vss v_1.5 a20m ierr f lush vss vcc vss init vss vcc vss pll1 rsv bclk stpclk ignne vss d16 d19 d7 d30 vcc vcc vref2 d24 d13 d20 vss vss d11 d3 d2 d14 vcc vcc d18 d9 d12 d10 vss rsv d17 vref3 d8 d5 vcc vcc d1 d6 d4 d15 vss vss berr vref4 d0 a34 vcc br1 reset2 a32 rsv a26 vss vss a29 a18 a27 a30 vcc vcc a24 a23 a33 a20 vss vss a31 vref5 a17 a22 vcc vcc a35 a25 edgctrl a19 vss vss reset a10 a5 a8 a4 bnr req1 req2 vtt rs1 vcc rs0 therm trip slp vcc vss vcc a21 vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc bsel1 bsel0 smi vid3 vcc vss a28 a3 a11 vref6 a14 vtt req0 lock vref7 aerr pwrgd rs2 rsv tms vcc vss vss vss a15 a13 a9 ap0 vtt a7 req4 req3 vtt hitm hit dbsy thrmdn thrmdp tck vid0 vid2 rsv vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vid1 vss a12 a16 a6 vtt ap1 vtt bpri defer vtt rp trdy drdy br0 ads trst tdi tdo pin side view an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a an am al ak aj ah ag af ae ad ac ab aa z y x w v u t s r q p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
52 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz table 29. signal listing in order by signal name (sheet 1 of 10) pin no. pin name signal group ak8 a3# agtl+ i/o ah12 a4# agtl+ i/o ah8 a5# agtl+ i/o an9 a6# agtl+ i/o al15 a7# agtl+ i/o ah10 a8# agtl+ i/o al9 a9# agtl+ i/o ah6 a10# agtl+ i/o ak10 a11# agtl+ i/o an5 a12# agtl+ i/o al7 a13# agtl+ i/o ak14 a14# agtl+ i/o al5 a15# agtl+ i/o an7 a16# agtl+ i/o ae1 a17# agtl+ i/o z6 a18# agtl+ i/o ag3 a19# agtl+ i/o ac3 a20# agtl+ i/o ae33 a20m# cmos input aj1 a21# agtl+ i/o ae3 a22# agtl+ i/o ab6 a23# agtl+ i/o ab4 a24# agtl+ i/o af6 a25# agtl+ i/o y3 a26# agtl+ i/o aa1 a27# agtl+ i/o ak6 a28# agtl+ i/o z4 a29# agtl+ i/o aa3 a30# agtl+ i/o ad4 a31# agtl+ i/o x6 a32# agtl+ i/o ac1 a33# agtl+ i/o w3 a34# agtl+ i/o af4 a35# agtl+ i/o an31 ads# agtl+ i/o ak24 aerr# agtl+ i/o al11 ap0# agtl+ i/o an13 ap1# agtl+ i/o w37 bclk system bus clock v4 berr# agtl+ i/o b36 binit# agtl+ i/o ah14 bnr# agtl+ i/o g33 bp2# agtl+ i/o e37 bp3# agtl+ i/o c35 bpm0# agtl+ i/o e35 bpm1# agtl+ i/o an17 bpri# agtl+ input an29 br0# agtl+ i/o x2 br1# 8 agtl+ input aj33 bsel0 power/other aj31 bsel1 power/other y33 clkref 7 power/other c37 cpupres# power/other w1 d0# agtl+ i/o t4 d1# agtl+ i/o n1 d2# agtl+ i/o m6 d3# agtl+ i/o u1 d4# agtl+ i/o s3 d5# agtl+ i/o t6 d6# agtl+ i/o j1 d7# agtl+ i/o s1 d8# agtl+ i/o p6 d9# agtl+ i/o q3 d10# agtl+ i/o m4 d11# agtl+ i/o q1 d12# agtl+ i/o l1 d13# agtl+ i/o n3 d14# agtl+ i/o u3 d15# agtl+ i/o h4 d16# agtl+ i/o r4 d17# agtl+ i/o p4 d18# agtl+ i/o h6 d19# agtl+ i/o l3 d20# agtl+ i/o g1 d21# agtl+ i/o f8 d22# agtl+ i/o g3 d23# agtl+ i/o k6 d24# agtl+ i/o e3 d25# agtl+ i/o e1 d26# agtl+ i/o table 29. signal listing in order by signal name (sheet 2 of 10) pin no. pin name signal group
datasheet 53 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz f12 d27# agtl+ i/o a5 d28# agtl+ i/o a3 d29# agtl+ i/o j3 d30# agtl+ i/o c5 d31# agtl+ i/o f6 d32# agtl+ i/o c1 d33# agtl+ i/o c7 d34# agtl+ i/o b2 d35# agtl+ i/o c9 d36# agtl+ i/o a9 d37# agtl+ i/o d8 d38# agtl+ i/o d10 d39# agtl+ i/o c15 d40# agtl+ i/o d14 d41# agtl+ i/o d12 d42# agtl+ i/o a7 d43# agtl+ i/o a11 d44# agtl+ i/o c11 d45# agtl+ i/o a21 d46# agtl+ i/o a15 d47# agtl+ i/o a17 d48# agtl+ i/o c13 d49# agtl+ i/o c25 d50# agtl+ i/o a13 d51# agtl+ i/o d16 d52# agtl+ i/o a23 d53# agtl+ i/o c21 d54# agtl+ i/o c19 d55# agtl+ i/o c27 d56# agtl+ i/o a19 d57# agtl+ i/o c23 d58# agtl+ i/o c17 d59# agtl+ i/o a25 d60# agtl+ i/o a27 d61# agtl+ i/o e25 d62# agtl+ i/o f16 d63# agtl+ i/o al27 dbsy# agtl+ i/o an19 defer# agtl+ input c33 dep0# agtl+ i/o table 29. signal listing in order by signal name (sheet 3 of 10) pin no. pin name signal group c31 dep1# agtl+ i/o a33 dep2# agtl+ i/o a31 dep3# agtl+ i/o e31 dep4# agtl+ i/o c29 dep5# agtl+ i/o e29 dep6# agtl+ i/o a29 dep7# agtl+ i/o an27 drdy# agtl+ i/o ag1 edgctrl 5 power/other ac35 ferr# cmos output ae37 flush# cmos input am22 gnd power/other am26 gnd power/other am30 gnd power/other am34 gnd power/other am6 gnd power/other an3 gnd power/other b12 gnd power/other b16 gnd power/other b20 gnd power/other b24 gnd power/other b28 gnd power/other b32 gnd power/other b4 gnd power/other b8 gnd power/other d18 gnd power/other d2 gnd power/other d22 gnd power/other d26 gnd power/other d30 gnd power/other d34 gnd power/other d4 gnd power/other e11 gnd power/other e15 gnd power/other e19 gnd power/other e7 gnd power/other f20 gnd power/other f24 gnd power/other f28 gnd power/other f32 gnd power/other table 29. signal listing in order by signal name (sheet 4 of 10) pin no. pin name signal group
54 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz f36 gnd power/other g5 gnd power/other h2 gnd power/other h34 gnd power/other k36 gnd power/other l5 gnd power/other m2 gnd power/other m34 gnd power/other p32 gnd power/other p36 gnd power/other a37 gnd power/other ab32 gnd power/other ac33 gnd power/other ac5 gnd power/other ad2 gnd power/other ad34 gnd power/other af32 gnd power/other af36 gnd power/other ag5 gnd power/other ah2 gnd power/other ah34 gnd power/other aj11 gnd power/other aj15 gnd power/other aj19 gnd power/other aj23 gnd power/other aj27 gnd power/other aj3 gnd power/other aj7 gnd power/other ak36 gnd power/other ak4 gnd power/other al1 gnd power/other al3 gnd power/other am10 gnd power/other am14 gnd power/other am18 gnd power/other q5 gnd power/other r34 gnd power/other t32 gnd power/other t36 gnd power/other u5 gnd power/other table 29. signal listing in order by signal name (sheet 5 of 10) pin no. pin name signal group v2 gnd power/other v34 gnd power/other x32 gnd power/other x36 gnd power/other y37 gnd power/other y5 gnd power/other z2 gnd power/other z34 gnd power/other al25 hit# agtl+ i/o al23 hitm# agtl+ i/o ae35 ierr# cmos output ag37 ignne# cmos input ag33 init# cmos input m36 lint0/intr cmos input l37 lint1/nmi cmos input ak20 lock# agtl+ i/o j33 picclk apic clock input j35 picd0 apic i/o l35 picd1 apic i/o w33 pll1 power/other u33 pll2 power/other a35 prdy# agtl+ output j37 preq# cmos input ak26 pwrgood cmos input ak18 req0# agtl+ i/o ah16 req1# agtl+ i/o ah18 req2# agtl+ i/o al19 req3# agtl+ i/o al17 req4# agtl+ i/o g37 reserved reserved for future use l33 reserved reserved for future use n33 reserved reserved for future use n35 reserved reserved for future use n37 reserved reserved for future use q33 reserved reserved for future use q35 reserved reserved for future use q37 reserved reserved for future use r2 reserved reserved for future use w35 reserved reserved for future use y1 reserved reserved for future use table 29. signal listing in order by signal name (sheet 6 of 10) pin no. pin name signal group
datasheet 55 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz ak30 reserved reserved for future use am2 6 reserved reserved for future use f10 reserved reserved for future use x2 br1# 8 agtl+ input ah4 reset# 2 agtl+ input x4 reset2# 2 agtl+ i/o an23 rp# agtl+ i/o ah26 rs0# agtl + input ah22 rs1# agtl+ input ak28 rs2# agtl+ input ac37 rsp# agtl+ input s35 rttctrl power/other e27 slewctrl power/other ah30 slp# cmos input aj35 smi# cmos input ag35 stpclk# cmos input al33 tck tap input an35 tdi tap input an37 tdo tap output al29 thermdn power/other al31 thermdp power/other ah28 thermtrip# cmos output ak32 tms tap input an25 trdy# agtl+ input an33 trst# tap input ad36 v cc 1.5 3 power/other z36 v cc 2.5 1 power/other ab36 v cc cmos power/other aa37 v cc core power/other aa5 v cc core power/other ab2 v cc core power/other ab34 v cc core power/other ad32 v cc core power/other ae5 v cc core power/other e5 v cc core power/other e9 v cc core power/other f14 v cc core power/other f2 v cc core power/other f22 v cc core power/other f26 v cc core power/other table 29. signal listing in order by signal name (sheet 7 of 10) pin no. pin name signal group f30 v cc core power/other f34 v cc core power/other f4 v cc core power/other h32 v cc core power/other h36 v cc core power/other j5 v cc core power/other k2 v cc core power/other k32 v cc core power/other k34 v cc core power/other m32 v cc core power/other n5 v cc core power/other p2 v cc core power/other p34 v cc core power/other r32 v cc core power/other r36 v cc core power/other s5 v cc core power/other t2 v cc core power/other t34 v cc core power/other v32 v cc core power/other v36 v cc core power/other w5 v cc core power/other x34 v cc core power/other y35 v cc core power/other z32 v cc core power/other af2 v cc core power/other af34 v cc core power/other ah24 v cc core power/other ah32 v cc core power/other ah36 v cc core power/other aj13 v cc core power/other aj17 v cc core power/other aj21 v cc core power/other aj25 v cc core power/other aj29 v cc core power/other aj5 v cc core power/other ak2 v cc core power/other ak34 v cc core power/other am12 v cc core power/other am16 v cc core power/other am20 v cc core power/other table 29. signal listing in order by signal name (sheet 8 of 10) pin no. pin name signal group
56 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz am24 v cc core power/other am28 v cc core power/other am32 v cc core power/other am4 v cc core power/other am8 v cc core power/other b10 v cc core power/other b14 v cc core power/other b18 v cc core power/other b22 v cc core power/other b26 v cc core power/other b30 v cc core power/other b34 v cc core power/other b6 v cc core power/other c3 v cc core power/other d20 v cc core power/other d24 v cc core power/other d28 v cc core power/other d32 v cc core power/other d36 v cc core power/other d6 v cc core power/other e13 v cc core power/other e17 v cc core power/other aj9 v cc core power/other e21 reserve power/other al35 vid0 power/other am36 vid1 power/other table 29. signal listing in order by signal name (sheet 9 of 10) pin no. pin name signal group al37 vid2 power/other aj37 vid3 power/other e33 v ref 0 power/other f18 v ref 1 power/other k4 v ref 2 power/other r6 v ref 3 power/other v6 v ref 4 power/other ad6 v ref 5 power/other ak12 v ref 6 power/other ak22 v ref 7 power/other ah20 v tt power/other ak16 v tt power/other al13 v tt power/other al21 v tt power/other an11 v tt power/other an15 v tt power/other g35 v tt power/other aa33 v tt 4 power/other aa35 v tt 4 power/other an21 v tt 4 power/other e23 v tt 4 power/other s33 v tt 4 power/other s37 v tt 4 power/other u35 v tt 4 power/other u37 v tt 4 power/other table 29. signal listing in order by signal name (sheet 10 of 10) pin no. pin name signal group
datasheet 57 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz table 30. signal listing in order by pin number (sheet 1 of 10) pin no. pin name signal group a3 d29# agtl+ i/o a5 d28# agtl+ i/o a7 d43# agtl+ i/o a9 d37# agtl+ i/o a11 d44# agtl+ i/o a13 d51# agtl+ i/o a15 d47# agtl+ i/o a17 d48# agtl+ i/o a19 d57# agtl+ i/o a21 d46# agtl+ i/o a23 d53# agtl+ i/o a25 d60# agtl+ i/o a27 d61# agtl+ i/o a29 dep7# agtl+ i/o a31 dep3# agtl+ i/o a33 dep2# agtl+ i/o a35 prdy# agtl+ output a37 gnd power/other aa1 a27# agtl+ i/o aa3 a30# agtl+ i/o aa5 v cc core power/other aa33 v tt 4 power/other aa35 v tt 4 power/other aa37 v cc core power/other ab2 v cc core power/other ab4 a24# agtl+ i/o ab6 a23# agtl+ i/o ab32 gnd power/other ab34 v cc core power/other ab36 v cc cmos power/other ac1 a33# agtl+ i/o ac3 a20# agtl+ i/o ac5 gnd power/other ac33 gnd power/other ac35 ferr# cmos output ac37 rsp# agtl+ input ad2 gnd power/other ad4 a31# agtl+ i/o ad6 v ref 5 power/other ad32 v cc core power/other ad34 gnd power/other ad36 v cc 1.5 3 power/other ae1 a17# agtl+ i/o ae3 a22# agtl+ i/o ae5 v cc core power/other ae33 a20m# cmos input ae35 ierr# cmos output ae37 flush# cmos input af2 v cc core power/other af4 a35# agtl+ i/o af6 a25# agtl+ i/o af32 gnd power/other af34 v cc core power/other af36 gnd power/other ag1 edgctrl 5 power/other ag3 a19# agtl+ i/o ag5 gnd power/other ag33 init# cmos input ag35 stpclk# cmos input ag37 ignne# cmos input ah2 gnd power/other ah4 reset# 2 agtl+ input ah6 a10# agtl+ i/o ah8 a5# agtl+ i/o ah10 a8# agtl+ i/o ah12 a4# agtl+ i/o ah14 bnr# agtl+ i/o ah16 req1# agtl+ i/o ah18 req2# agtl+ i/o ah20 v tt power/other ah22 rs1# agtl+ input ah24 v cc core power/other ah26 rs0# agtl + input ah28 thermtrip# cmos output ah30 slp# cmos input ah32 v cc core power/other ah34 gnd power/other ah36 v cc core power/other aj1 a21# agtl+ i/o aj3 gnd power/other table 30. signal listing in order by pin number (sheet 2 of 10) pin no. pin name signal group
58 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz aj5 v cc core power/other aj7 gnd power/other aj9 v cc core power/other aj11 gnd power/other aj13 v cc core power/other aj15 gnd power/other aj17 v cc core power/other aj19 gnd power/other aj21 v cc core power/other aj23 gnd power/other aj25 v cc core power/other aj27 gnd power/other aj29 v cc core power/other aj31 bsel1 power/other aj33 bsel0 power/other aj35 smi# cmos input aj37 vid3 power/other ak2 v cc core power/other ak4 gnd power/other ak6 a28# agtl+ i/o ak8 a3# agtl+ i/o ak10 a11# agtl+ i/o ak12 v ref 6 power/other ak14 a14# agtl+ i/o ak16 v tt power/other ak18 req0# agtl+ i/o ak20 lock# agtl+ i/o ak22 v ref 7 power/other ak24 aerr# agtl+ i/o ak26 pwrgood cmos input ak28 rs2# agtl+ input ak30 reserved reserved for future use ak32 tms tap input ak34 v cc core power/other ak36 gnd power/other al1 gnd power/other al3 gnd power/other al5 a15# agtl+ i/o al7 a13# agtl+ i/o al9 a9# agtl+ i/o table 30. signal listing in order by pin number (sheet 3 of 10) pin no. pin name signal group al11 ap0# agtl+ i/o al13 v tt power/other al15 a7# agtl+ i/o al17 req4# agtl+ i/o al19 req3# agtl+ i/o al21 v tt power/other al23 hitm# agtl+ i/o al25 hit# agtl+ i/o al27 dbsy# agtl+ i/o al29 thermdn power/other al31 thermdp power/other al33 tck tap input al35 vid0 power/other al37 vid2 power/other am2 6 reserved reserved for future use am4 v cc core power/other am6 gnd power/other am8 v cc core power/other am10 gnd power/other am12 v cc core power/other am14 gnd power/other am16 v cc core power/other am18 gnd power/other am20 v cc core power/other am22 gnd power/other am24 v cc core power/other am26 gnd power/other am28 v cc core power/other am30 gnd power/other am32 v cc core power/other am34 gnd power/other am36 vid1 power/other an3 gnd power/other an5 a12# agtl+ i/o an7 a16# agtl+ i/o an9 a6# agtl+ i/o an11 v tt power/other an13 ap1# agtl+ i/o an15 v tt power/other an17 bpri# agtl+ input table 30. signal listing in order by pin number (sheet 4 of 10) pin no. pin name signal group
datasheet 59 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz an19 defer# agtl+ input an21 v tt 4 power/other an23 rp# agtl+ i/o an25 trdy# agtl+ input an27 drdy# agtl+ i/o an29 br0# agtl+ i/o an31 ads# agtl+ i/o an33 trst# tap input an35 tdi tap input an37 tdo tap output b2 d35# agtl+ i/o b4 gnd power/other b6 v cc core power/other b8 gnd power/other b10 v cc core power/other b12 gnd power/other b14 v cc core power/other b16 gnd power/other b18 v cc core power/other b20 gnd power/other b22 v cc core power/other b24 gnd power/other b26 v cc core power/other b28 gnd power/other b30 v cc core power/other b32 gnd power/other b34 v cc core power/other b36 binit# agtl+ i/o c1 d33# agtl+ i/o c3 v cc core power/other c5 d31# agtl+ i/o c7 d34# agtl+ i/o c9 d36# agtl+ i/o c11 d45# agtl+ i/o c13 d49# agtl+ i/o c15 d40# agtl+ i/o c17 d59# agtl+ i/o c19 d55# agtl+ i/o c21 d54# agtl+ i/o c23 d58# agtl+ i/o table 30. signal listing in order by pin number (sheet 5 of 10) pin no. pin name signal group c25 d50# agtl+ i/o c27 d56# agtl+ i/o c29 dep5# agtl+ i/o c31 dep1# agtl+ i/o c33 dep0# agtl+ i/o c35 bpm0# agtl+ i/o c37 cpupres# power/other d2 gnd power/other d4 gnd power/other d6 v cc core power/other d8 d38# agtl+ i/o d10 d39# agtl+ i/o d12 d42# agtl+ i/o d14 d41# agtl+ i/o d16 d52# agtl+ i/o d18 gnd power/other d20 v cc core power/other d22 gnd power/other d24 v cc core power/other d26 gnd power/other d28 v cc core power/other d30 gnd power/other d32 v cc core power/other d34 gnd power/other d36 v cc core power/other e1 d26# agtl+ i/o e3 d25# agtl+ i/o e5 v cc core power/other e7 gnd power/other e9 v cc core power/other e11 gnd power/other e13 v cc core power/other e15 gnd power/other e17 v cc core power/other e19 gnd power/other e21 reserve power/other e23 v tt 4 power/other e25 d62# agtl+ i/o e27 slewctrl power/other e29 dep6# agtl+ i/o table 30. signal listing in order by pin number (sheet 6 of 10) pin no. pin name signal group
60 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz e31 dep4# agtl+ i/o e33 v ref 0 power/other e35 bpm1# agtl+ i/o e37 bp3# agtl+ i/o f2 v cc core power/other f4 v cc core power/other f6 d32# agtl+ i/o f8 d22# agtl+ i/o f10 reserved reserved for future use f12 d27# agtl+ i/o f14 v cc core power/other f16 d63# agtl+ i/o f18 v ref 1 power/other f20 gnd power/other f22 v cc core power/other f24 gnd power/other f26 v cc core power/other f28 gnd power/other f30 v cc core power/other f32 gnd power/other f34 v cc core power/other f36 gnd power/other g1 d21# agtl+ i/o g3 d23# agtl+ i/o g5 gnd power/other g33 bp2# agtl+ i/o g35 v tt power/other g37 reserved reserved for future use h2 gnd power/other h4 d16# agtl+ i/o h6 d19# agtl+ i/o h32 v cc core power/other h34 gnd power/other h36 v cc core power/other j1 d7# agtl+ i/o j3 d30# agtl+ i/o j5 v cc core power/other j33 picclk apic clock input j35 picd0 apic i/o j37 preq# cmos input table 30. signal listing in order by pin number (sheet 7 of 10) pin no. pin name signal group k2 v cc core power/other k4 v ref 2 power/other k6 d24# agtl+ i/o k32 v cc core power/other k34 v cc core power/other k36 gnd power/other l1 d13# agtl+ i/o l3 d20# agtl+ i/o l5 gnd power/other l33 reserved reserved for future use l35 picd1 apic i/o l37 lint1/nmi cmos input m2 gnd power/other m4 d11# agtl+ i/o m6 d3# agtl+ i/o m32 v cc core power/other m34 gnd power/other m36 lint0/intr cmos input n1 d2# agtl+ i/o n3 d14# agtl+ i/o n5 v cc core power/other n33 reserved reserved for future use n35 reserved reserved for future use n37 reserved reserved for future use p2 v cc core power/other p4 d18# agtl+ i/o p6 d9# agtl+ i/o p32 gnd power/other p34 v cc core power/other p36 gnd power/other q1 d12# agtl+ i/o q3 d10# agtl+ i/o q5 gnd power/other q33 reserved reserved for future use q35 reserved reserved for future use q37 reserved reserved for future use r2 reserved reserved for future use r4 d17# agtl+ i/o r6 v ref 3 power/other r32 v cc core power/other table 30. signal listing in order by pin number (sheet 8 of 10) pin no. pin name signal group
datasheet 61 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz r34 gnd power/other r36 v cc core power/other s1 d8# agtl+ i/o s3 d5# agtl+ i/o s5 v cc core power/other s33 v tt 4 power/other s35 rttctrl power/other s37 v tt 4 power/other t2 v cc core power/other t4 d1# agtl+ i/o t6 d6# agtl+ i/o t32 gnd power/other t34 v cc core power/other t36 gnd power/other u1 d4# agtl+ i/o u3 d15# agtl+ i/o u5 gnd power/other u33 pll2 power/other u35 v tt 4 power/other u37 v tt 4 power/other v2 gnd power/other v4 berr# agtl+ i/o v6 v ref 4 power/other v32 v cc core power/other v34 gnd power/other table 30. signal listing in order by pin number (sheet 9 of 10) pin no. pin name signal group v36 v cc core power/other w1 d0# agtl+ i/o w3 a34# agtl+ i/o w5 v cc core power/other w33 pll1 power/other w35 reserved reserved for future use w37 bclk system bus clock x2 br1# 8 agtl+ input x4 reset2# 2 agtl+ i/o x6 a32# agtl+ i/o x32 gnd power/other x34 v cc core power/other x36 gnd power/other y1 reserved reserved for future use y3 a26# agtl+ i/o y5 gnd power/other y33 clkref 7 power/other y35 v cc core power/other y37 gnd power/other z2 gnd power/other z4 a29# agtl+ i/o z6 a18# agtl+ i/o z32 v cc core power/other z34 gnd power/other z36 v cc 2.5 1 power/other table 30. signal listing in order by pin number (sheet 10 of 10) pin no. pin name signal group
62 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 6.0 boxed processor specifications the intel ? pentium ? iii processor for the pga370 socket is also offered as an intel boxed processor. intel boxed processors are intended for system integrators who build systems from motherboards and standard components. the boxed pentium iii processor for the pga370 socket will be supplied with an unattached fan heatsink. this section documents motherboard and system requirements for the fan heatsink that will be supplied with the boxed pentium iii processor. this section is particularly important for oems that manufacture motherboards for system integrators. unless otherwise noted, all figures in this section are dimensioned in inches. figure 22 shows a mechanical representation of the boxed intel pentium iii processor for the pga370 socket in the flip chip pin grid array (fc-pga) package. note: drawings in this section reflect only the specifications on the intel boxed processor product. these dimensions should not be used as a generic keep-out zone for all heatsinks. it is the system designers responsibility to consider their proprietary solution when designing to the required keep- out zone on their system platform and chassis. refer to the intel ? pentium ? iii processor enabling functional specification for further guidance. contact your local intel sales representative for this document. 6.1 mechanical specifications this section documents the mechanical specifications of the boxed pentium iii processor fan heatsink. 6.1.1 boxed processor thermal cooling solution dimensions the boxed processor ships with an unattached fan heatsink that has an integrated clip. clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. note that the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. the dimensions for the boxed processor with integrated fan heatsink are shown in figure 23 and figure 24 . there are two versions of the fan heatsink. the larger cooling solution (depicted on the right of figure 23 and figure 24 is required for pentium iii processors at frequencies of 866 mhz and above. general spatial specifications are also outlined in table 31 . all dimensions are in inches. figure 22. conceptual boxed intel ? pentium ? iii processor for the pga370 socket
datasheet 63 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz the boxed processor fan heatsink is asymmetrical in that the mechanical step feature (specified in figure 25 ) must sit over the sockets cam. note that the step allows the heatsink to securely interface with the processor in order to meet thermal requirements. figure 23. side view of space requirements for the boxed processor figure 24. side view of space requirements for the boxed processor table 31. boxed processor fan heatsink spatial dimensions dimensions (inches) min typ max fan heatsink length 2.52 fan heatsink for >= 866mhz length 2.68 fan heatsink height 1.76 fan heatsink for >= 866mhz height 1.78 fan heatsink width 2.00 fan heatsink for >= 866mhz width 2.65 fan heatsink height above motherboard .29 fan heatsink for >= 866mhz height above motherboard .29 2. 52 1.78 1.76 2.68 1.78 1.76 2.00 1.78 2.65 1.93
64 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 6.1.2 boxed processor heatsink weight the boxed processor thermal cooling solution will not weigh more than 180 grams. 6.1.3 boxed processor thermal cooling solution clip the boxed processor thermal solution requires installation by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370-pin socket zif socket. motherboards designed for use by system integrators should take care to consider the implications of clip installation and potential scraping of the motherboard pcb underneath the 370-pin socket attach tabs. motherboard components should not be placed too close to the 370-pin socket attach tabs in a way that interferes with the installation of the boxed processor thermal cooling solution (see figure 26 for specification). figure 25. dimensions of mechanical step feature in heatsink base 0.472 0.043 figure 26. clip keepout requirements for boxed intel ? pentium ? iii processors pga 370 & pga370s pga 370 & pga370s all dimensions are minimum unless otherwise specified no components 0 . 122" max. height off mb emi pads 0 . 060" max. height off mb 0 . 127" max. height off mb 1 . 022" max. height off mb 1 . 38 2 . 528 . 005 ref . pga370 design spec. 1 . 44 1 . 44 1 . 54 1 . 83 4x . 400 4x . 450 4x . 175 4x . 258 . 210 . 672 + - 1 . 570 1 . 570 1.315 nom 1.315 nom 1 . 68 . 672 . 290
datasheet 65 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 6.2 boxed processor requirements 6.2.1 fan heatsink power supply the boxed processor's fan heatsink requires a +12 v power supply. a fan power cable is attached to the fan and will draw power from a power header on the motherboard. the power cable connector and pinout are shown in figure 27 . motherboards must provide a matched power header to support the boxed processor. table 32 contains specifications for the input and output signals at the fan heatsink connector. the cable length is 7.0 inches (0.25"). the fan heatsink outputs a sense signal, which is an open-collector output, that pulses at a rate of two pulses per fan revolution. a motherboard pull-up resistor provides voh to match the motherboard-mounted fan speed monitor requirements, if applicable. use of the sense signal is optional. if the sense signal is not used, pin 3 of the connector should be tied to gnd. the power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. the power header identification and location should be documented in the motherboard documentation or on the motherboard. figure 28 shows the recommended location of the fan power connector relative to the pga370 socket. the motherboard power header should be positioned within 4.00 inches from the center of the pga370 socket. figure 27. boxed processor fan heatsink power cable connector description table 32. fan heatsink power and signal specifications description min typ max +12 v: 12 volt fan power supply 7 v 12 v 13.8 v ic: fan current draw 100 ma sense: sense frequency (motherboard should pull this pin up to appropriate v cc with resistor) 2 pulses per fan revolution pin signal straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. waldom/molex p/n 22-01-3037 or equivalent. match with straight pin, friction lock header on motherboard waldom/molex p/n 22-23-2031, amp p/n 640456-3, or equivalent. 1 2 3 gnd +12v sense 123
66 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 6.3 thermal specifications this section describes the cooling requirements of the thermal cooling solution utilized by the boxed processor. 6.3.1 boxed processor cooling requirements the boxed processor is cooled with a fan heatsink. the boxed processor fan heatsink will keep the processor core at the specified tjunction (see table 24 ), provided airflow through the fan heatsink is unimpeded. it is recommended that the air temperature entering the fan inlet is below 45c (measured at 0.3 inches above the fan hub). airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. figure 29 shows the specification for all boxed pentium iii processor fan heatsinks as 0.20 clearance in all directions. (this is inclusive of the fan heatsink used on boxed pentium iii processors at 700 mhz and higher.) figure 28. motherboard power header placement relative to the boxed intel ? pentium ? iii processor 0.10" socket 7 0.10" r = 4.00 pga370
datasheet 67 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz figure 29. thermal airspace requirement for all boxed intel ? pentium ? iii processor fan heatsinks in the pga370 socket .20 .20
68 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 7.0 processor signal description this section provides an alphabetical listing of all the intel ? pentium ? iii processor signals. the tables at the end of this section summarize the signals by direction: output, input, and i/o. 7.1 alphabetical signals reference table 33. signal description (sheet 1 of 8) name type description a[35:3]# i/o the a[35:3]# (address) signals define a 2 36 -byte physical memory address space. when ads# is active, these pins transmit the address of a transaction; when ads# is inactive, these pins transmit transaction type information. these signals must connect the appropriate pins of all agents on the processor system bus. the a[35:24]# signals are parity-protected by the ap1# parity signal, and the a[23:3]# signals are parity-protected by the ap0# parity signal. on the active-to-inactive transition of reset#, the processors sample the a[35:3]# pins to determine their power-on configuration. see the intel ? pentium ? ii processor developers manual for details. a20m# i if the a20m# (address-20 mask) input signal is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1 mb boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. ads# i/o the ads# (address strobe) signal is asserted to indicate the validity of the transaction address on the a[35:3]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. this signal must connect the appropriate pins on all processor system bus agents. aerr# i/o the aerr# (address parity error) signal is observed and driven by all processor system bus agents, and if used, must connect the appropriate pins on all processor system bus agents. aerr# observation is optionally enabled during power-on configuration; if enabled, a valid assertion of aerr# aborts the current transaction. if aerr# observation is disabled during power-on configuration, a central agent may handle an assertion of aerr# as appropriate to the error handling architecture of the system. ap[1:0]# i/o the ap[1:0]# (address parity) signals are driven by the request initiator along with ads#, a[35:3]#, req[4:0]#, and rp#. ap1# covers a[35:24]#, and ap0# covers a[23:3]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the appropriate pins of all processor system bus agents. bclk i the bclk (bus clock) signal determines the bus frequency. all processor system bus agents must receive this signal to drive their outputs and latch their inputs on the bclk rising edge. all external timing parameters are specified with respect to the bclk signal.
datasheet 69 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz berr# i/o the berr# (bus error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor system bus agents, and must connect the appropriate pins of all such agents, if used. however, pentium iii processors do not observe assertions of the berr# signal. berr# assertion conditions are configurable at a system level. assertion options are defined by the following options: ? enabled or disabled. ? asserted optionally for internal errors along with ierr#. ? asserted optionally by the request initiator of a bus transaction after it observes an error. ? asserted by any bus agent when it observes an error in a bus transaction. binit# i/o the binit# (bus initialization) signal may be observed and driven by all processor system bus agents, and if used must connect the appropriate pins of all such agents. if the binit# driver is enabled during power on configuration, binit# is asserted to signal any bus condition that prevents reliable future information. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, all bus state machines are reset and any data which was in transit is lost. all agents reset their rotating id for bus arbitration to the state after reset, and internal count information is lost. the l1 and l2 caches are not affected. if binit# observation is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. bnr# i/o the bnr# (block next request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents might need to request a bus stall at the same time, bnr# is a wire-or signal which must connect the appropriate pins of all processor system bus agents. in order to avoid wire-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is activated on specific clock edges and sampled on specific clock edges. bp[3:2]# i/o the bp[3:2]# (breakpoint) signals are outputs from the processor that indicate the status of breakpoints. bpm[1:0]# i/o the bpm[1:0]# (breakpoint monitor) signals are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpri# i the bpri# (bus priority request) signal is used to arbitrate for ownership of the processor system bus. it must connect the appropriate pins of all processor system bus agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. table 33. signal description (sheet 2 of 8) name type description
70 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz br0# br1# i/o i the br0# and br1# (bus request) pins drive the breq[1:0]# signals in the system. the breq[1:0]# signals are interconnected in a rotating manner to individual processor pins. the table below gives the rotating interconnect between the processor and bus signals. bsel[1:0] i/o these signals are used to select the system bus frequency. a bsel[1:0] = 01 selects a 100 mhz system bus frequency and a bsel[1:0] = 11 selects a 133 mhz system bus frequency. the frequency is determined by the processor(s), chipset, and frequency synthesizer capabilities. all system bus agents must operate at the same frequency. the pentium iii processor for the pga370 socket operates at 100 mhz and 133 mhz system bus frequencies. individual processors will only operate at their specified front side bus (fsb) frequency. either 100 mhz or 133 mhz, not both. on motherboards which support operation at either 66 mhz or 100 mhz, a bsel[1:0] = x0 will select a 66 mhz system bus frequency. 66 mhz operation is not support by the pentium iii processor for the pga370 socket; therefore, bsel0 is ignored. these signals must be pulled up to 2.5 v or 3.3v with 1 k w resistors and provided as a frequency selection signal to the clock driver/synthesizer. if the system motherboard is not capable of operating at 133 mhz, it should ground the bsel1 signal and generate a 100 mhz system bus frequency. see section 2.8.2 for implementation examples. clkref i the clkref input is a filtered 1.25v supply voltage for the processor pll. a voltage divider and decoupling solution is provided by the motherboard. see the design guide for implementation details. table 33. signal description (sheet 3 of 8) name type description during power-up configuration, the central agent must assert the br0# bus signal. all symmetric agents sample their br[1:0]# pins on active-to-inactive transition of reset#. the pin on which the agent samples an active level determines its symmetric agent id. all agents then configure their pins to match the appropriate bus signal protocol, as shown below. br0# (i/o) and br1# signals rotating interconnect bus signal agent 0 pins agent 1 pins breq0# br0# br1# breq1# br1# br0# br[1:0]# signal agent ids pin sampled active in reset# agent id br0# 0 br1# 3
datasheet 71 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz cpupres# o the cpupres# signal is defined to allow a system design to detect the presence of a terminator device or processor in a pga370 socket. combined with the vid combination of vid[3:0]= 1111 (see section 2.6 ), a system can determine if a socket is occupied, and whether a processor core is present. see the table below for states and values for determining the presence of a device. d[63:0]# i/o the d[63:0]# (data) signals are the data signals. these signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. dbsy# i/o the dbsy# (data bus busy) signal is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all processor system bus agents. defer# i the defer# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or i/o agent. this signal must connect the appropriate pins of all processor system bus agents. dep[7:0]# i/o the dep[7:0]# (data bus ecc protection) signals provide optional ecc protection for the data bus. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate pins of all processor system bus agents which use them. the dep[7:0]# signals are enabled or disabled for ecc protection during power on configuration. drdy# i/o the drdy# (data ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-cycle data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all processor system bus agents. edgctrl o the edgctrl input adjusts the edge rate of agtl+ output buffers for previous processors and should be pulled up to v cc core with a 51 w 5% resistor. see the platform design guide for implementation details. this signal is not used by the pentium iii processor. ferr# o the ferr# (floating-point error) signal is asserted when the processor detects an unmasked floating-point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms-dos*-type floating-point error reporting. table 33. signal description (sheet 4 of 8) name type description pga370 socket occupation truth table signal value status cpupres# vid[3:0] 0 anything other than 1111 processor core installed in the pga370 socket. cpupres# vid[3:0] 0 1111 terminator device installed in the pga370 socket (i.e., no core present). cpupres# vid[3:0] 1 any value pga370 socket not occupied.
72 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz flush# i when the flush# input signal is asserted, processors write back all data in the modified state from their internal caches and invalidate all internal cache lines. at the completion of this operation, the processor issues a flush acknowledge transaction. the processor does not cache any new data while the flush# signal remains asserted. flush# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. on the active-to-inactive transition of reset#, each processor samples flush# to determine its power-on configuration. see the p6 family of processors hardware developers manual for details. hit# hitm# i/o i/o the hit# (snoop hit) and hitm# (hit modified) signals convey transaction snoop operation results, and must connect the appropriate pins of all processor system bus agents. any such agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. ierr# o the ierr# (internal error) signal is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the processor system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#, binit#, or init#. ignne# i the ignne# (ignore numeric error) signal is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. init# i the init# (initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (l1 or l2) caches or floating-point registers. each processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). lint[1:0] i the lint[1:0] (local apic interrupt) signals must connect the appropriate pins of all apic bus agents, including all processors and the core logic or i/o apic component. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the intel ? pentium ? processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# i/o the lock# signal indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor system bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the processor system bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. table 33. signal description (sheet 5 of 8) name type description
datasheet 73 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz picclk i the picclk (apic clock) signal is an input clock to the processor and core logic or i/o apic which is required for operation of all processors, core logic, and i/o apic components on the apic bus. picd[1:0] i/o the picd[1:0] (apic data) signals are used for bidirectional serial message passing on the apic bus, and must connect the appropriate pins of all processors and core logic or i/o apic components on the apic bus. pll1, pll2 i all pentium iii processors have an internal analog pll clock generator that requires a quiet power supply. pll1 and pll2 are inputs to this pll and must be connected to v cc core through a low pass filter that minimizes jitter. see the platform design guide for implementation details. prdy# o the prdy (probe ready) signal is a processor output used by debug tools to determine processor debug readiness. preq# i the preq# (probe request) signal is used by debug tools to request debug operation of the processors. pwrgood i the pwrgood (power good) signal is processor input. the processor requires this signal to be a clean indication that the clocks and power supplies (v cc core , etc.) are stable and within their specifications. clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. the figure below illustrates the relationship of pwrgood to other system signals. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. it must also meet the minimum pulse width specification in table 13 , and be followed by a 1 ms reset# pulse. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# i/o the req[4:0]# (request command) signals must connect the appropriate pins of all processor system bus agents. they are asserted by the current bus owner over two clock cycles to define the currently active transaction type. reset# i asserting the reset# signal resets all processors to known states and invalidates their l1 and l2 caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least one millisecond after v cc core and clk have reached their proper specifications. on observing active reset#, all processor system bus agents will deassert their outputs within two clocks. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the p6 family of processors hardware developers manual for details. the processor may have its outputs tristated via power-on configuration. otherwise, if init# is sampled active during the active-to-inactive transition of reset#, the processor will execute its built-in self-test (bist). whether or not bist is executed, the processor will begin program execution at the power on reset vector (default 0_ffff_fff0h). reset# must connect the appropriate pins of all processor system bus agents. reset2# i the reset2# pin is provided for compatibility with other intel architecture processors. the pentium iii processor does not use the reset2# pin. refer to the platform design guide for the proper connections of this signal. rp# i/o the rp# (request parity) signal is driven by the request initiator, and provides parity protection on ads# and req[4:0]#. it must connect the appropriate pins of all processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this definition allows parity to be high when all covered signals are high. rs[2:0]# i the rs[2:0]# (response status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. table 33. signal description (sheet 6 of 8) name type description
74 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz rsp# i the rsp# (response parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect the appropriate pins of all processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. rttctrl i the rttctrl input signal provides agtl+ termination control. the pentium iii processor samples this input to sense the presence of motherboard agtl+ termination. see the platform design guide for implementation details. slewctrl i the slewctrl input signal provides agtl+ slew rate control. the pentium iii processor samples this input to determine the slew rate for agtl+ signals when it is the driving agent. see the platform design guide for implementation details. slp# i the slp# (sleep) signal, when asserted in stop-grant state, causes processors to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will recognize only assertions of the slp#, stpclk#, and reset# signals while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and apic processor core units. smi# i the smi# (system management interrupt) signal is asserted asynchronously by system logic. on accepting a system management interrupt, processors save the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. stpclk# i the stpclk# (stop clock) signal, when asserted, causes processors to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and apic units. the processor continues to snoop bus transactions and latch interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units, services pending interrupts while in the stop-grant state, and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck i the tck (test clock) signal provides the clock input for the processor test bus (also known as the test access port). tdi i the tdi (test data in) signal transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo o the tdo (test data out) signal transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. thermdn o thermal diode cathode. used to calculate core (junction) temperature. see section 4.1 . thermdp i thermal diode anode. used to calculate core (junction) temperature. see section 4.1 . thermtrip# o the processor protects itself from catastrophic overheating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds approximately 135 c. this is signaled to the system by the thermtrip# (thermal trip) pin. once activated, the signal remains latched, and the processor stopped, until reset# goes active. there is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a reset# pulse will reset the processor and execution will continue. if the temperature has not dropped below the trip level, the processor will continue to drive thermtrip# and remain stopped. tms i the tms (test mode select) signal is a jtag specification support signal used by debug tools. table 33. signal description (sheet 7 of 8) name type description
datasheet 75 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz 7.2 signal summaries table 34 through table 37 list attributes of the processor output, input, and i/o signals. trdy# i the trdy# (target ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all processor system bus agents. trst# i the trst# (test reset) signal resets the test access port (tap) logic. trst# must be driven low during power on reset. vid[3:0] o the vid[3:0] (voltage id) pins can be used to support automatic selection of power supply voltages. these pins are not signals, but are either an open circuit or a short circuit to v ss on the processor. the combination of opens and shorts defines the voltage required by the processor. the vid pins are needed to cleanly support voltage specification variations on processors. see table 2 for definitions of these pins. the power supply must supply the voltage that is requested by these pins, or disable itself. v core det o the v core det pin indicate the type of processor core present. this pin will float for 2.0v v cc core based processor and will be shorted to v ss for the pentium iii processor. v cc 1.5 i the v cc 1.5 v input pin provides the termination voltage for cmos signals interfacing to the processor. the pentium iii processor reroutes the 1.5v input to the v cc cmos output via the package. the supply for v cc 1.5 v must be the same one used to supply v tt . v cc 2.5 i the v cc 2.5 v input pin provides the termination voltage for cmos signals interfacing to processors which require 2.5v termination on the cmos signals. this signal is not used by the pentium iii processor. v cc cmos o the v cc cmos pin provides the cmos voltage for use by the platform and is used for terminating cmos signals that interface to the processor. v ref i the v ref input pins supply the agtl+ reference voltage, which is typically 2/3 of v tt . v ref is used by the agtl+ receivers to determine if a signal is a logical 0 or a logical 1. table 33. signal description (sheet 8 of 8) name type description table 34. output signals name active level clock signal group cpupres# low asynch power/other edgctrl n/a asynch power/other ferr# low asynch cmos output ierr# low asynch cmos output prdy# low bclk agtl+ output tdo high tck tap output thermtrip# low asynch cmos output v core det n/a asynch power/other vid[3:0] n/a asynch power/other
76 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz note: 1. synchronous assertion with active tdry# ensures synchronization. table 35. input signals name active level clock signal group qualified a20m# low asynch cmos input always 1 bclk high system bus clock always bpri# low bclk agtl+ input always br1# low bclk agtl+ input always defer# low bclk agtl+ input always flush# low asynch cmos input always 1 ignne# low asynch cmos input always 1 init# low asynch cmos input always 1 intr high asynch cmos input apic disabled mode lint[1:0] high asynch cmos input apic enabled mode nmi high asynch cmos input apic disabled mode picclk high apic clock always preq# low asynch cmos input always pwrgood high asynch cmos input always reset# low bclk agtl+ input always rs[2:0]# low bclk agtl+ input always rsp# low bclk agtl+ input always rttctrl n/a asynch power/other slewctrl n/a asynch power/other slp# low asynch cmos input during stop-grant state smi# low asynch cmos input stpclk# low asynch cmos input tck high tap input tdi high tck tap input tms high tck tap input trst# low asynch tap input trdy# low bclk agtl+ input
datasheet 77 pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz table 36. input/output signals (single driver) name active level clock signal group qualified a[35:3]# low bclk agtl+ i/o ads#, ads#+1 ads# low bclk agtl+ i/o always ap[1:0]# low bclk agtl+ i/o ads#, ads#+1 bp[3:2]# low bclk agtl+ i/o always bpm[1:0]# low bclk agtl+ i/o always br0# low bclk agtl+ i/o always bsel[1:0] high asynch power/other always d[63:0]# low bclk agtl+ i/o drdy# dbsy# low bclk agtl+ i/o always dep[7:0]# low bclk agtl+ i/o drdy# drdy# low bclk agtl+ i/o always lock# low bclk agtl+ i/o always req[4:0]# low bclk agtl+ i/o ads#, ads#+1 rp# low bclk agtl+ i/o ads#, ads#+1 table 37. input/output signals (multiple driver) name active level clock signal group qualified aerr# low bclk agtl+ i/o ads#+3 berr# low bclk agtl+ i/o always binit# low bclk agtl+ i/o always bnr# low bclk agtl+ i/o always hit# low bclk agtl+ i/o always hitm# low bclk agtl+ i/o always picd[1:0] high picclk apic i/o always
78 datasheet pentium ? iii processor for the pga370 socket at 500 mhz to 933 mhz this page is intentionally blank. end of datasheet.

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